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參數(shù)資料
| 型號(hào)： | CY7C1355A |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 194K |
| 代理商： | CY7C1355A |
CY7C1019B/
CY7C10191B
Document #: 38-05026 Rev. *A
Page 5 of 9
Write Cycle No. 1 (CE Controlled)[12, 13]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
Notes:
12. Data I/O is high impedance if OE = VIH.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
CE
ADDRESS
WE
DATA I/O
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 14
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1356A | Memory |
| CY7C1367A-225AJC | x18 Synchronous SRAM |
| CY7C1367A-225BGC | x18 Synchronous SRAM |
| CY7C1368B | Memory |
| CY7C1370B-133AC | x36 Fast Synchronous SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1355A-100AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 7.5ns 100-Pin TQFP |
| CY7C1355A-100BGC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 7.5ns 119-Pin BGA |
| CY7C1355A-100BZC | 制造商:Cypress Semiconductor 功能描述:8M- 256KX36 3.3V FLOW-THROUGH-NOBL SRAM - Bulk |
| CY7C1355A-117AI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 7ns 100-Pin TQFP |
| CY7C1355A-133AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 6.5ns 100-Pin TQFP |
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