- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358698 > CY7C1362B-225AJC (CYPRESS SEMICONDUCTOR CORP) BACKSHELL, MDR, 50WAY, METAL; For use with:Mini D Ribbon 101XX-6000 EC Plug Connectors; Material:Aluminum; Colour:Nickel; Connector type:Backshell; Ways, No. of:50 RoHS Compliant: Yes PDF資料下載
參數(shù)資料
| 型號： | CY7C1362B-225AJC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | BACKSHELL, MDR, 50WAY, METAL; For use with:Mini D Ribbon 101XX-6000 EC Plug Connectors; Material:Aluminum; Colour:Nickel; Connector type:Backshell; Ways, No. of:50 RoHS Compliant: Yes |
| 中文描述： | 512K X 18 CACHE SRAM, 2.8 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 9/34頁 |
| 文件大小： | 895K |
| 代理商： | CY7C1362B-225AJC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
CY7C1360B
CY7C1362B
Document #: 38-05291 Rev. *C
Page 9 of 34
CY7C1362B–Pin Definitions
Name
TQFP
3-Chip
Enable
TQFP
2-Chip
Enable
BGA
fBGA
I/O
Description
A
0
, A
1
, A
37,36,32,
33,34,35,
43,44,45,
46,47,48,
49,50,80,
81,82,99,
100
37,36,32,
33,34,35,
44,45,46,
47,48,49,
50,80,81,
82,92,99,
100
P4,N4,
A2,C2,
R2,T2,
A3,B3,
C3,T3,
A5,B5,
C5,T5,
A6,B6,
C6,R6,
T6
R6,P6,A2,
A10,A11,
B2,B10,P3,
P4,P8,P9,
P10,P11,
R3,R4,R8,
R9,R10,
R11
Input-
Synchronous
Address Inputs used to select one of the 512K
address locations
. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3[2]
are sampled active. A
1
, A
0
are fed
to the two-bit counter..
BW
A,
BW
B
93,94
93,94
G3,L5
B5,A4
Input-
Synchronous
Byte Write Select Inputs, active LOW
. Qualified
with BWE to conduct Byte Writes to the SRAM.
Sampled on the rising edge of CLK.
GW
88
88
H4
B7
Input-
Synchronous
Global Write Enable Input, active LOW
. When
asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written,
regardless of the values on BW
X
and BWE).
BWE
87
87
M4
A7
Input-
Synchronous
Byte Write Enable Input, active LOW
. Sampled
on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.
CLK
89
89
K4
B6
Input-
Clock
Clock Input
. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during
a burst operation.
CE
1
98
98
E4
A3
Input-
Synchronous
Chip Enable 1 Input, active LOW
. Sampled on
the rising edge of CLK. Used in conjunction with
CE
2
and CE
3[2]
to select/deselect the device.
ADSP is ignored if CE
1
is HIGH.
CE
2
97
97
B2
B3
Input-
Synchronous
Chip Enable 2 Input, active HIGH
. Sampled on
the rising edge of CLK. Used in conjunction with
CE
1
and CE
3[2]
to select/deselect the device.
CE
3 [2]
92
-
-
A6
Input-
Synchronous
Chip Enable 3 Input, active LOW
. Sampled on
the rising edge of CLK. Used in conjunction with
CE
1
and
CE
2
to select/deselect the device. Not
available for AJ package version. Not connected
for BGA. Where referenced, CE
3[2]
is assumed
active throughout this document for BGA.
OE
86
86
F4
B8
Input-
Asynchronous
Output Enable, asynchronous input, active
LOW
. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and
act as input data pins. OE is masked during the first
clock of a Read cycle when emerging from a
deselected state.
ADV
83
83
G4
A9
Input-
Synchronous
Advance Input signal, sampled on the rising
edge of CLK, active LOW
. When asserted, it
automatically increments the address in a burst
cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1362B-225AI | Plastic Connector Backshell; Connector Shell Size:Black; Enclosure Material:Polyester; Enclosure Color:Black; Features:For: 0.050" D-Miniature D Ribbon Connectors; Leaded Process Compatible:No; No. of Positions:50 RoHS Compliant: No |
| CY7C1362B-225AJI | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| CY7C1362B-225BGC | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| CY7C1362B-225AC | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| CY7C1362B | Plastic Connector Backshell; Enclosure Material:Plastic; Enclosure Color:Beige; Leaded Process Compatible:No; No. of Positions:26; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1362C-166AJXC | 功能描述:靜態(tài)隨機存取存儲器 512Kx18 3.3V COM Sync PL 1CD 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1362C-166AJXCT | 功能描述:IC SRAM 9MBIT 166MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:移動 SDRAM 存儲容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應商設備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1362C-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 3.5ns 100-Pin TQFP |
| CY7C1362C-166BZC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1362C-200AJXC | 功能描述:靜態(tài)隨機存取存儲器 512Kx18 3.3V COM Sync PL 1CD 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。