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| 型號(hào)： | CY7C1381C-100BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 8.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁(yè)數(shù)： | 10/36頁(yè) |
| 文件大?。?/td> | 564K |
| 代理商： | CY7C1381C-100BGI |
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CY7C1381C
CY7C1383C
Document #: 38-05238 Rev. *B
Page 10 of 36
ADSP
84
A4
B9
Input-
Synchronous
Address Strobe from Processor,
sampled on the rising edge of CLK,
active LOW
. When asserted LOW,
addresses presented to the device are
captured in the address registers. A
[1:0]
are
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE
1
is deasserted HIGH
Address Strobe from Controller,
sampled on the rising edge of CLK,
active LOW
. When asserted LOW,
addresses presented to the device are
captured in the address registers. A
[1:0]
are
also loaded into the burst counter. When
ADSP and ADSC are both asserted, only
ADSP is recognized.
ADSC
85
B4
A8
Input-
Synchronous
ZZ
64
T7
H11
Input-
Asynchronous
ZZ “sleep” Input, active HIGH
. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
DQ
s
58,59,62,63,68,
69,72,73,8,9,12,
13,
18,19,22,23
P7,K7,G7,E7,F6
,H6,L6,N6,D1,H
1,L1,N1,E2,G2,
K2,M2
J10,K10,
L10,M10,
D11,E11,
F11,G11,J1,K1,
L1,M1,
D2,E2,F2,
G2
I/O-
Synchronous
Bidirectional Data I/O lines
. As inputs,
they feed into an on-chip data register that
is triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQ
and DQP
are placed
in a tri-state condition.The outputs are
automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
DQP
[A:B]
74,24
D6,P2
C11,N1
I/O-
Synchronous
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQ
s
.
During write sequences, DQP
[A:B]
is
controlled by BW
[A:B]
correspondingly.
MODE
31
R3
R1
Input-Static
Selects Burst Order
. When tied to GND
selects linear burst sequence. When tied to
V
DD
or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
CY7C1383C:Pin Definitions
(continued)
Name
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
I/O
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1381C-100BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1381C-100BZI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V SYNC-FT SRAM - Bulk |
| CY7C1381D-100AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1381D-100AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1381D-100AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM Sync FT 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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