參數(shù)資料
型號(hào): CY7C1382BV25-133BGC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 512K x 36 / 1 Mb x 18 Pipelined SRAM
中文描述: 1M X 18 CACHE SRAM, 4.2 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, BGA-119
文件頁(yè)數(shù): 6/30頁(yè)
文件大?。?/td> 860K
代理商: CY7C1382BV25-133BGC
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
6
TMS
Test Mode Select
Synchronous
JTAG serial
clock
Power Supply
This pin controls the Test Access Port state machine. Sampled on the rising
edge of TCK (BGA Only).
Serial clock to the JTAG circuit (BGA Only).
TCK
V
DD
Power supply inputs to the core of the device. Should be connected to 3.3V
–5% +10% power supply.
Ground for the core of the device. Should be connected to ground of the sys-
tem.
Power supply for the I/O circuitry. Should be connected to a 3.3V –5% +10%
power supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
No Connects.
V
SS
Ground
V
DDQ
I/O Power
Supply
I/O Ground
-
V
SSQ
NC
Pin Definitions
Name
I/O
Description
相關(guān)PDF資料
PDF描述
CY7C1381C 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117AC 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117AI 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117BGC 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-117BGI 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
相關(guān)代理商/技術(shù)參數(shù)
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