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參數(shù)資料
| 型號(hào)： | CY7C1383C-117AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 1M X 18 STANDARD SRAM, 7.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 564K |
| 代理商： | CY7C1383C-117AC |
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CY7C1381C
CY7C1383C
Document #: 38-05238 Rev. *B
Page 7 of 36
ADSC
85
B4
A8
Input-
Synchronous
Address Strobe from Controller, sampled
on the rising edge of CLK, active LOW
.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
BWE
87
M4
A7
Input-
Synchronous
Byte Write Enable Input, active LOW
.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
ZZ
64
T7
H11
Input-
Asynchronous
ZZ “sleep” Input, active HIGH
. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
DQ
s
52,53,56,57,58,
59,62,63,68,69,
72,73,74,75,78,
79,2,3,6,7,8,9,
12,13,18,19,22,
23,24,25,28,29
K6,L6,M6,N6,K7
,L7,N7,P7,E6,F
6,G6,H6,D7,E7,
G7,H7,D1,E1,G
1,H1,E2,F2,G2,
H2,K1,L1,N1,P1
,K2,L2,M2,N2
M11,L11,K11,
J11,J10,K10,
L10,M10,D10,
E10,F10,G10,
D11,E11,F11,
G11,D1,E1,
F1,G1,D2,E2,
F2,G2,J1,K1,
L1,M1,J2,
K2,L2,M2,
I/O-
Synchronous
Bidirectional Data I/O lines
. As inputs, they
feed into an on-chip data register that is
triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQ
and DQP
are placed
in a tri-state condition.The outputs are
automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
DQP
[A:D]
51,80,1,30
P6,D6,D2,P2
N11,C11,C1,N1
I/O-
Synchronous
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQ
s
.
During write sequences, DQP
[A:D]
is
controlled by BW
[A:D]
correspondingly.
MODE
31
R3
R1
Input-Static
Selects Burst Order
. When tied to GND
selects linear burst sequence. When tied to
V
DD
or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
V
DD
15,41,65,91
J2,C4,J4,R4,J6
D4,D8,E4,
E8,F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
Power Supply
Power supply inputs to the core of the
device
.
CY7C1381C–Pin Definitions
(continued)
Name
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1383C-117AI | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1383C-117BGC | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1383C-117BGI | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1383C-117BZC | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1383C-117BZI | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
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