參數(shù)資料
型號(hào)： CY7C1383C-117BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
中文描述： 1M X 18 STANDARD SRAM, 7.5 ns, PBGA119
封裝： 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁數(shù)： 14/36頁
文件大小： 564K
代理商： CY7C1383C-117BGC
CY7C1381C
CY7C1383C
Document #: 38-05238 Rev. *B
Page 14 of 36
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
, CE
, CE
3[2]
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW.
.
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
[ 3, 4, 5, 6, 7]
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
60
2t
CYC
Unit
mA
ns
ns
ns
ns
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to snooze current
ZZ Inactive to exit snooze current
2t
CYC
2t
CYC
0
Cycle Description
ADDRESS
Used
CE
1
H
CE
2
CE
3
X
ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselected Cycle,
Power-down
None
X
L
X
L
X
X
X
L-H Tri-State
Deselected Cycle,
Power-down
None
L
L
X
L
L
X
X
X
X
L-H Tri-State
Deselected Cycle,
Power-down
None
L
X
H
L
L
X
X
X
X
L-H Tri-State
Deselected Cycle,
Power-down
None
L
L
X
L
H
L
X
X
X
L-H Tri-State
Deselected Cycle,
Power-down
None
X
X
X
L
H
L
X
X
X
L-H Tri-State
Snooze Mode, Pow-
er-down
None
X
X
X
H
X
X
X
X
X
X
Tri-State
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H..
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
9
External
External
External
External
External
Next
Next
L
L
L
L
L
X
X
H
H
H
H
H
X
X
L
L
L
L
L
X
X
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
L
L
L
H
H
X
X
X
X
X
L
L
X
X
L
H
H
H
H
L
H
X
L
H
L
H
L-H Q
L-H Tri-State
L-H D
L-H Q
L-H Tri-State
L-H Q
L-H Tri-State
相關(guān)PDF資料
PDF描述
CY7C1383C-117BGI 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-117BZC 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1383C-117BZI 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
CY7C1381C-100BZI CAPACITOR, CHIP, CERAMIC
CY7C1381C-100BGC 18-Mb (512K x 36/1M x 18) Flow-Through SRAM
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