參數(shù)資料
型號(hào): CY7C1383DV25-100BZI
廠(chǎng)商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
中文描述: 1M X 18 CACHE SRAM, 8.5 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁(yè)數(shù): 14/28頁(yè)
文件大小: 952K
代理商: CY7C1383DV25-100BZI
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E
Page 14 of 28
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; V
DD
= 2.5V ±0.125V unless otherwise noted)
[12]
Parameter
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
Min.
2.0
2.1
Max.
Unit
V
V
V
V
V
V
μA
I
OH
= –1.0 mA, V
DDQ
= 2.5V
I
OH
= –100 μA, V
DDQ
= 2.5V
I
OL
= 8.0 mA, V
DDQ
= 2.5V
I
OL
= 100 μA
0.4
0.2
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 2.5V
1.7
–0.3
–5
V
DD
+ 0.3
0.7
5
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
CY7C1381DV25/
CY7C1381FV25
(512K x 36)
000
01011
101001
000001
100101
00000110100
1
CY7C1383DV25/
CY7C1383FV25
(1 Mbit x 18)
000
01011
101001
000001
010101
00000110100
1
Description
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18) 119-BGA
Device Width (23:18) 165-FBGA
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Describes the version number
Reserved for internal use.
Defines the memory type and architecture
Defines the memory type and architecture
Defines the width and density
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Bit Size (x36)
3
1
32
85
89
Bit Size (x18)
3
1
32
85
89
Instruction Bypass
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Note
12.All voltages referenced to V
SS
(GND).
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CY7C1383DV25-100BZXC 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
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