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參數(shù)資料
| 型號(hào)： | CY7C1411AV18-250BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture |
| 中文描述： | 4M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 10/28頁(yè) |
| 文件大?。?/td> | 1143K |
| 代理商： | CY7C1411AV18-250BZXI |
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CY7C1411AV18
CY7C1426AV18
CY7C1413AV18
CY7C1415AV18
Document Number: 38-05614 Rev. *C
Page 10 of 28
Write Cycle Descriptions
(CY7C1411AV18 and CY7C1413AV18)
[2, 10]
BWS
0
/NWS
0
BWS
1
/NWS
1
L
K
K
Comments
L
L–H
–
During the Data portion of a Write sequence
:
CY7C1411AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1413AV18
both bytes (D
[17:0]
) are written into the device.
L-H During the Data portion of a Write sequence
:
CY7C1411AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1413AV18
both bytes (D
[17:0]
) are written into the device.
–
During the Data portion of a Write sequence
:
CY7C1411AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain
unaltered,
CY7C1413AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain
unaltered.
L–H During the Data portion of a Write sequence
:
CY7C1411AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain
unaltered,
CY7C1413AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain
unaltered.
–
During the Data portion of a Write sequence
:
CY7C1411AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1413AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain
unaltered.
L–H During the Data portion of a Write sequence
:
CY7C1411AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will
remain unaltered,
CY7C1413AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain
unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
H
H
L–H
–
Note:
10.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
,
and BWS
3
can be altered on different
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
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