參數(shù)資料
型號： CY7C1413AV18-200BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
中文描述： 2M X 18 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù)： 11/28頁
文件大?。?/td> 1143K
代理商： CY7C1413AV18-200BZI
CY7C1411AV18
CY7C1426AV18
CY7C1413AV18
CY7C1415AV18
Document Number: 38-05614 Rev. *C
Page 11 of 28
Write Cycle Descriptions
[2, 10]
(CY7C1415AV18)
BWS
0
BWS
1
BWS
2
BWS
3
L
L
K
K
Comments
L
L
L–H
–
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written
into the device.
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are written
into the device.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written
into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is written
into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written
into the device. D
[26:0]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is written
into the device. D
[26:0]
will remain unaltered.
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
L
L
L
L
–
L–H
L
H
H
H
L–H
–
L
H
H
H
–
L–H
H
L
H
H
L–H
–
H
L
H
H
–
L–H
H
H
L
H
L–H
–
H
H
L
H
–
L–H
H
H
H
L
L–H
H
H
H
L
–
L–H
H
H
H
H
H
H
H
H
L–H
–
–
L–H
Write Cycle Descriptions
[2, 10]
(CY7C1426AV18)
BWS
0
K
K
Comments
L
L
H
H
L–H
–
L–H
–
–
During the Data portion of a Write sequence, the single byte (D
[8:0]
) is written into the device.
During the Data portion of a Write sequence, the single byte (D
[8:0]
) is written into the device.
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
L–H
–
L–H
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相關(guān)PDF資料
PDF描述
CY7C1413AV18-200BZXC 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
CY7C1413AV18-200BZXI 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
CY7C1413AV18-250BZC 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
CY7C1413AV18-250BZI 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
CY7C1413AV18-250BZXC 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1413AV18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1413AV18-250BZCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 2MX18 0.45NS 165FBGA - Bulk
CY7C1413AV18-250BZCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1413AV18250BZXC 制造商:Cypress Semiconductor 功能描述:
CY7C1413AV18-250BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 QDR II Burst 4 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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