參數(shù)資料
型號(hào)： CY7C1470V33-250BZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： ECONOLINE: RQS & RQD - 1kVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 80%
中文描述： 2M X 36 ZBT SRAM, 3 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
文件頁數(shù)： 18/27頁
文件大?。?/td> 382K
代理商： CY7C1470V33-250BZXC
PRELIMINARY
CY7C1470V25
CY7C1472V25
CY7C1474V25
Document #: 38-05290 Rev. *E
Page 18 of 27
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +3.6V
DC to Outputs in Tri-State................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage....................................–0.5V to V
DD
+ 0.5V
Electrical Characteristics
Over the Operating Range
[12, 13]
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
V
DD
V
DDQ
2.5V–5%/+5%
1.7V to
V
DD
Parameter
V
DD
V
DDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
2.375
2.375
1.7
2.0
1.6
Max.
2.625
V
DD
1.9
Unit
V
V
V
V
V
V
V
V
V
V
V
μ
A
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DD
= Min., I
OH
=
1.0 mA, V
DDQ
= 2.5V
V
DD
= Min., I
OH
= –100
μ
A,V
DDQ
= 1.8V
V
DD
= Min., I
OL
=
1.0 mA, V
DDQ
= 2.5V
V
DD
= Min., I
OL
= 100
μ
A,V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
GND
≤
V
I
≤
V
DDQ
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
0.4
0.2
V
IH
Input HIGH Voltage
[12]
1.7
1.26
–0.3
–0.3
–5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.7
0.36
5
V
IL
Input LOW Voltage
[12]
I
X
Input Load Current ex-
cept ZZ and MODE
Input Current of MODE Input = V
SS
–5
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
mA
mA
mA
Input = V
DD
Input = V
SS
Input = V
DD
30
Input Current of ZZ
–30
5
5
I
OZ
I
DD
Output Leakage Current GND
≤
V
I
≤
V
DDQ,
Output Disabled
V
DD
Operating Supply
V
DD
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
–5
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speed grades
450
450
400
200
200
200
120
I
SB1
Automatic CE
Power-down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = f
MAX
=
1/t
CYC
I
SB2
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Max. V
DD
, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
0.3V,
f = 0
Max. V
DD
, Device Deselected,
V
IN
≤
0.3V or V
IN
> V
DDQ
0.3V,
f = f
MAX
= 1/t
CYC
I
SB3
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speed grades
200
200
200
135
mA
mA
mA
mA
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
Max. V
DD
, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = 0
Shaded areas contain advance information.
Notes:
12.Overshoot: V
(AC) < V
+1.5V (Pulse width less than t
/2), undershoot: V
(AC)> –2V (Pulse width less than t
CYC
/2).
13.T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
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