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參數(shù)資料
| 型號(hào)： | CY7C166 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 16K x 4 Static RAM |
| 中文描述： | 16K的× 4靜態(tài)RAM |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 171K |
| 代理商： | CY7C166 |
CY7C164
CY7C166
Document #: 38-05025 Rev. **
Page 3 of 9
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 5ns
< 5 ns
5V
OUTPUT
R1 481
R2
255
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
THVENIN EQUIVALENT
ALL INPUT PULSES
C164–5
C164–6
167
Switching Characteristics Over the Operating Range[5]
7C164-15
7C166-15
7C164-20
7C166-20
7C164-25
7C166-25
7C164-35
7C166-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
20
25
35
ns
tAA
Address to Data Valid
15
20
25
35
ns
tOHA
Output Hold from Address Change
3
5
ns
tACE
CE LOW to Data Valid
15
20
25
35
ns
tDOE
OE LOW to Data Valid
7C166
10
12
15
ns
tLZOE
OE LOW to Low Z
7C166
3
ns
tHZOE
OE HIGH to High Z
7C166
8
10
12
ns
tLZCE
CE LOW to Low Z[6]
3
5
ns
tHZCE
CE HIGH to High Z[6, 7]
8
10
15
ns
tPU
CE LOW to Power-Up
0
ns
tPD
CE HIGH to Power-Down
15
20
ns
WRITE CYCLE[8]
tWC
Write Cycle Time
15
20
25
ns
tSCE
CE LOW to Write End
12
15
20
25
ns
tAW
Address Set-Up to Write End
12
15
20
25
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
12
15
20
ns
tSD
Data Set-Up to Write End
10
15
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z[6]
5
ns
tHZWE
WE LOW to High Z[6, 7]
7
10
ns
Notes:
5.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6.
At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested.
7.
tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
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