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參數(shù)資料
| 型號(hào)： | CY7C186-25DC |
| 英文描述： | x8 SRAM |
| 中文描述： | x8的SRAM |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 194K |
| 代理商： | CY7C186-25DC |
CY7C1019B/
CY7C10191B
Document #: 38-05026 Rev. *A
Page 5 of 9
Write Cycle No. 1 (CE Controlled)[12, 13]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
Notes:
12. Data I/O is high impedance if OE = VIH.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
CE
ADDRESS
WE
DATA I/O
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 14
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| CY7C186-35DC | x8 SRAM |
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| CY7C186-45PC | x8 SRAM |
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| CY7C186-55PC | x8 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CY7C186-25PI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C186-45PC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C18655PC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C186A-20DMB | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 64K-Bit 8K x 8 20ns 28-Pin CDIP |
| CY7C186A-45DMB | 制造商:Cypress Semiconductor 功能描述: |
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