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參數資料
| 型號： | CY7C198-15LC |
| 英文描述： | x8 SRAM |
| 中文描述： | x8的SRAM |
| 文件頁數： | 4/9頁 |
| 文件大?。?/td> | 194K |
| 代理商： | CY7C198-15LC |
CY7C1019B/
CY7C10191B
Document #: 38-05026 Rev. *A
Page 4 of 9
Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter
Description
Conditions
Min.
Max.
Unit
VDR
VCC for Data Retention
No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0
V
ICCDR
Data Retention Current
300
A
tCDR
[3]
Chip Deselect to Data Retention Time
0
ns
tR
Operation Recovery Time
200
s
Data Retention Waveform
3.0V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
Switching Waveforms
Read Cycle No. 1[9, 10]
Read Cycle No. 2 (OE Controlled)[10, 11]
Notes:
9.
Device is continuously selected. OE, CE = VIL.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
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| CY7C198-25DMB | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 25ns 28-Pin CDIP |
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| CY7C198-35DMB | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 256K-Bit 32K x 8 35ns 28-Pin CDIP |
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