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參數(shù)資料
| 型號(hào)： | CY7C43686AV-10AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| 中文描述： | 16K X 36 BI-DIRECTIONAL FIFO, 8 ns, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-128 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 644K |
| 代理商： | CY7C43686AV-10AC |
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 18 of 40
t
FSH
t
BEH
t
SPMH
t
SDH
t
SENH
t
SPH
t
SKEW1[20]
Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH
Hold Time, SPM after MRS1 and MRS2 HIGH
Hold Time, FS0/SD after CLKA
↑
Hold Time, FS1/SEN after CLKA
↑
Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH
Skew Time between CLKA
↑
and CLKB
↑
and CLKA
↑
and
CLKC
↑
for EFA/ORA, EFB/ORB, FFA/IRA, and FFC/IRC
Skew Time between CLKA
↑
and CLKB
↑
and CLKA
↑
and
CLKC
↑
for AEA, AEB, AFA, AFC
Access Time, CLKA
↑
to A
0
–
35
and CLKB
↑
to B
0
–
17
Propagation Delay Time, CLKA
↑
to FFA/IRA and CLKC
↑
to
FFC/IRC
Propagation Delay Time, CLKA
↑
to EFA/ORA and CLKB
↑
to
EFB/ORB
Propagation Delay Time, CLKA
↑
to AEA and CLKB
↑
to AEB
Propagation Delay Time, CLKA
↑
to AFA and CLKC
↑
to AFC
Propagation Delay Time, CLKA
↑
to MBF1 LOW or MBF2 HIGH
and CLKB
↑
to MBF2 LOW or MBF1 HIGH
Propagation Delay Time, CLKA
↑
to B
0
–
17[21]
and CLKC
↑
to
A
0
–
35[22]
Propagation Delay Time, MBA to A
0
–
35
valid and MBB to B
0
–
17
Valid
Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW,
AFA HIGH, FFA / IRA LOW, EFB /ORB LOW and MBF1 HIGH
and MRS2 or PRS2 LOW to AEA LOW, AFC HIGH, FFC / IRC
LOW, EFA /ORA LOW and MBF2 HIGH
Enable Time, CSA or W/RA LOW to A
0
–
35
Active and CSB LOW
and RENB HIGH to B
0
–
17
Active
Disable Time, CSA or W/RA HIGH to A
0
–
35
at High Impedance
and CSB HIGH or RENB LOW to B
0
–
17
at High Impedance
Retransmit Recovery Time
1
1
1
0
0
1
5
1
1
1
0
0
1
5
2
2
2
0
0
2
ns
ns
ns
ns
ns
ns
ns
7.5
t
SKEW2[20]
7
8
12
ns
t
A
t
WFF
1
1
6
6
1
1
8
8
3
2
10
10
ns
ns
t
REF
1
6
1
8
2
10
ns
t
PAE
t
PAF
t
PMF
1
1
0
6
6
6
1
1
0
8
8
8
1
1
0
10
10
12
ns
ns
ns
t
PMR
1
7
2
11
3
12
ns
t
MDV
1
6
2
9
3
11
ns
t
RSF
1
6
1
10
1
15
ns
t
EN
1
6
2
8
2
10
ns
t
DIS
1
5
1
6
1
8
ns
t
RTR
Notes:
20. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
21. Writing data to the Mail1 register when the B
0
–
17
outputs are active and MBB is HIGH.
22. Writing data to the Mail2 register when the A
0
–
35
outputs are active and MBA is HIGH.
90
90
90
ns
Switching Characteristics
Over the Operating Range (continued)
Parameter
Description
7C43646/
66/86AV
–
7
Min.
7C43646/
66/86AV
–
10
Min.
7C43646/
66/86AV
–
15
Min.
Unit
Max.
Max.
Max.
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