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| 型號(hào)： | CY8C27243-24SI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 外設(shè)及接口 |
| 英文描述： | PSoC Mixed Signal Array |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PDSO20 |
| 封裝： | 0.300 INCH, LEAD FREE, MO-119, SOIC-20 |
| 文件頁(yè)數(shù)： | 28/44頁(yè) |
| 文件大?。?/td> | 542K |
| 代理商： | CY8C27243-24SI |
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August 3, 2004
Document No. 38-12012 Rev. *I
28
CY8C27x43 Final Data Sheet
3. Electrical Specifications
3.4
AC Electrical Characteristics
3.4.1
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40
°
C
≤
T
A
≤
85
°
C, or 3.0V to 3.6V and -40
°
C
≤
T
A
≤
85
°
C, respectively. Typical parameters apply to 5V and 3.3V at 25
°
C and
are for design guidance only.
Figure 3-3. PLL Lock Timing Diagram
Table 3-18. AC Chip-Level Specifications
Symbol
F
IMO
F
CPU1
F
CPU2
F
48M
Description
Min
Typ
Max
Units
MHz
Notes
Internal Main Oscillator Frequency
23.4
24
24.6
a
24.6
a,b
12.3
b,c
49.2
a,b,d
Trimmed. Utilizing factory trim values.
CPU Frequency (5V Nominal)
0.93
24
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived fromInternal Main Oscillator with appropriate trimfor Vdd range.
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimmng for operation at 3.3V.
d. See the individual user module data sheets for information on maximumfrequencies for user modules.
MHz
Trimmed. Utilizing factory trim values.
CPU Frequency (3.3V Nominal)
0.93
12
MHz
Trimmed. Utilizing factory trim values.
Digital PSoC Block Frequency
0
48
MHz
Refer to the AC Digital Block Specifications
below.
F
24M
F
32K1
F
32K2
Digital PSoC Block Frequency
0
24
24.6
b, d
64
MHz
Internal Low Speed Oscillator Frequency
15
32
kHz
External Crystal Oscillator
–
32.768
–
kHz
Accuracy is capacitor and crystal dependent.
50% duty cycle.
Multiple (x732) of crystal frequency.
F
PLL
Jitter24M2
T
PLLSLEW
T
PLLSLEWS-
LOW
T
OS
T
OSACC
PLL Frequency
–
23.986
–
MHz
24 MHz Period Jitter (PLL)
PLL Lock Time
–
0.5
–
–
600
10
ps
ms
PLL Lock Time for Low Gain Setting
0.5
–
50
ms
External Crystal Oscillator Startup to 1%
–
1700
2620
3800
ms
External Crystal Oscillator Startup to 100 ppm
–
2800
ms
The crystal oscillator frequency is within 100 ppmof its
final value by the end of the T
osacc
period. Correct
operation assumes a properly loaded 1 uW maximum
drive level 32.768 kHz crystal. 3.0V
≤
Vdd
≤
5.5V, -40
o
C
≤
T
A
≤
85
o
C.
Jitter32k
T
XRST
DC24M
Step24M
Fout48M
32 kHz Period Jitter
External Reset Pulse Width
–
10
100
–
ns
μ
s
%
kHz
MHz
–
24 MHz Duty Cycle
24 MHz Trim Step Size
48 MHz Output Frequency
40
–
46.8
50
50
48.0
60
–
49.2
a,c
Trimmed. Utilizing factory trim values.
Jitter24M1
F
MAX
T
RAMP
24 MHz Period Jitter (IMO)
Maximum frequency of signal on row input or row output.
–
–
600
–
ps
MHz
12.3
Supply Ramp Time
0
–
–
μ
s
24 MHz
F
PLL
PLL
Enable
T
PLLSLEW
PLL
Gain
0
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