參數(shù)資料
型號: CY8CLED01D01-56LTXI
廠商: Cypress Semiconductor Corp
文件頁數(shù): 22/55頁
文件大小: 0K
描述: IC MCU 16K FLASH 1K SRAM 56VQFN
特色產(chǎn)品: PowerPSoC? Embedded Power Controller
標(biāo)準(zhǔn)包裝: 260
系列: PowerPSoC® CY8CLED
核心處理器: M8C
芯體尺寸: 8-位
速度: 24MHz
連通性: DALI,DMX512,I²C,IrDA,SPI,UART/USART
外圍設(shè)備: LED,LVD,POR,PWM,WDT
輸入/輸出數(shù): 14
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-VFQFN 裸露焊盤
包裝: 托盤
配用: 428-2882-ND - KIT STARTER POWERPSOC LIGHTING
428-2281-ND - KIT EVAL POWERPSOC LIGHTING
428-2270-ND - KIT STARTER DEMO LIGHTING
其它名稱: 428-2966
CY8CLED04D01, CY8CLED04D02, CY8CLED04G01
CY8CLED03D01, CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *P
Page 29 of 55
14. Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED04D0X, CY8CLED04G01, CY8CLED03D0X,
CY8CLED03G01, CY8CLED02D01, and CY8CLED01D01 of the PowerPSoC device family. For the most up to date electrical
specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com/powerpsoc.
Specifications for Industrial rated devices are valid for –40 °C
T
A 85 °C, TJ 115 °C and for Extended Temperature rated devices
for –40 °C
T
A 105 °C, TJ 125 °C, except where noted.
14.1 Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. Not all user guidelines are production tested.
Table 14-1. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
Notes
TSTG
Storage temperature
–55
+115
°C
Higher storage temperatures
reduces data retention time.
Recommended storage
temperature is 0 °C to 50 °C.
TA
Ambient temperature with power applied
–40
+85
+105
°C
TJ 115 °C (industrial rated)
TJ 125 °C (extended
temperature rated)
VDD,
AVDD,
GDVDD
Supply voltage on VDD, AVDD, and
GDVDD
–0.5
+6.0
V
Relative to VSS, AVSS, and
GDVSS respectively
VIO
DC input voltage
VSS – 0.5
VDD + 0.5
V
Applies only to GPIO and FN0
pins
VIO2
DC voltage applied to tristate
VSS – 0.5
VDD + 0.5
V
VFET
Maximum voltage from power Switch
(SWx) to Power FET Ground (PGNDx)
V
PGNDx is connected to GDVSS
VREGIN
Maximum voltage on SREGHVIN Pin
relative to VSS
V
VCSP,VCSN
Maximum voltage applied to CSA pins
relative to VSS
–0.5
V
VSENSE
Maximum input differential voltage across
CSA input
–1.0
1.0
V
IMAIO
Maximum current into any port pin
configured as analog driver
–50
+50
mA
IMIO
Maximum current into any port and
function pin
–25
+50
mA
LU
Latch up current
200
mA
JESD78A Conformal
ESD
Electrostatic discharge voltage
2000
V
Human Body Model ESD.
SRREGIN
Ramp rate for the SREGHVIN pin
32
V/
s
SRCSP
Ramp rate for the CSPx pins
3.2
V/
s
SRHVDD-FLB High voltage supply ramp rate for floating
load buck configuration
15
V/ms
For other topologies, to enable
operation with faster ramp rates,
or if the LED string voltage is
< 6.5 V, see the PowerPSoC
Technical Reference Manual.
SRVDD-EXT
External VDD supply ramp rate (VDD,
AVDD, and GDVDD pins)
0.2
V/
s
Applies only when powered by a
source other than the Built-in
Switching Regulator
Note
13. Stresses beyond the “Absolute Maximum Ratings” on page 29 may cause permanent damage to the device. You must ensure that the absolute maximum ratings are
NEVER exceeded. Functional operation is not implied under any conditions beyond the “Electrical Characteristics” on page 30 onwards. Extended exposure to
“Absolute Maximum Ratings” on page 29 may affect reliability of the device.
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