參數(shù)資料
型號(hào)： CYNSE70256
英文描述： Network Processing
中文描述： 網(wǎng)絡(luò)處理
文件頁(yè)數(shù)： 7/126頁(yè)
文件大小： 3302K
代理商： CYNSE70256
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 7 of 126
LIST OF TABLES
Table 5-1. CYNSE70032 Signal Description .......................................................................................11
Table 7-1. Register Overview ..............................................................................................................13
Table 7-2. Search Successful Register Description ............................................................................14
Table 8-1. Command Register Description ..........................................................................................14
Table 9-1. Information Register Description ........................................................................................15
Table 9-2. Read Burst Register Description ........................................................................................16
Table 9-3. Write Burst Register Description ........................................................................................16
Table 9-4. NFA Register ......................................................................................................................16
Table 10-1. Bit Position Match .............................................................................................................17
Table 12-1. Command Codes ..............................................................................................................18
Table 12-2. Command Parameters .....................................................................................................19
Table 12-3. Read Command Parameters ............................................................................................19
Table 12-4. Read Address Format for Data Array, Mask Array, or SRAM ..........................................20
Table 12-5. Read Address Format for Internal Registers ....................................................................21
Table 12-6. Read Address Format for Data and Mask Arrays .............................................................21
Table 12-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write) ....................22
Table 12-8. Write Address Format for Internal Registers ....................................................................22
Table 12-9. Write Address Format for Data and Mask Array (Burst Write) .........................................23
Table 13-1. Search Latency from Instruction to SRAM Access Cycle ................................................26
Table 13-2. Shift of SSF and SSV from SADR ....................................................................................26
Table 13-3. HIT/MISS Assumption ......................................................................................................26
Table 13-4. Search latency from Instruction to SRAM Access Cycle ..................................................31
Table 13-5. Shift of SSF and SSV from SADR ....................................................................................31
Table 13-6. Hit/Miss Assumption .........................................................................................................32
Table 13-7. Search Latency from Instruction to SRAM Access Cycle .................................................45
Table 13-8. Shift of SSF and SSV from SADR ....................................................................................45
Table 13-9. Search Latency from Instruction to SRAM Access Cycle .................................................47
Table 13-10. Shift of SSF and SSV from SADR ..................................................................................47
Table 13-11. Hit/Miss Assumptions .....................................................................................................48
Table 13-12. Search Latency from Instruction to SRAM Access Cycle ...............................................53
Table 13-13. Shift of SSF and SSV from SADR ..................................................................................53
Table 13-14. Hit/Miss Assumptions .....................................................................................................54
Table 13-15. Search Latency from Instruction to SRAM Access Cycle ...............................................68
Table 13-16. Shift of SSF and SSV from SADR ..................................................................................68
Table 13-17. Search Latency from Instruction to SRAM Access Cycle ...............................................70
Table 13-18. Shift of SSF and SSV from SADR ..................................................................................70
Table 13-19. Hit/Miss Assumptions .....................................................................................................71
Table 13-20. Search Latency from Instruction to SRAM Access Cycle ...............................................76
Table 13-21. Shift of SSF and SSV from SADR ..................................................................................76
Table 13-22. Hit/Miss Assumptions .....................................................................................................77
Table 13-23. Search Latency from Instruction to SRAM Access Cycle ...............................................90
Table 13-24. Shift of SSF and SSV from SADR ..................................................................................90
Table 13-25. SRAM Write Cycle Latency from Second Cycle of Learn Instruction .............................95
Table 15-1. SRAM Bus Address ..........................................................................................................99
Table 18-1. Supported Operations ....................................................................................................115
Table 19-1. DC Electrical Characteristics for CYNSE70032 .............................................................116
Table 19-2. Operating Conditions for CYNSE70032 .........................................................................116
Table 18-2. TAP Device ID Register .................................................................................................116
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