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參數(shù)資料
| 型號： | CYW2330ZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 封裝： | 0.173 INCH, TSSOP-20 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 228K |
| 代理商： | CYW2330ZI |
CYW2330
PRELIMINARY
Document #: 38-07239 Rev. **
Page 6 of 13
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data as described in Table 1.
Notes:
2.
t1–t6 = t > 50 ns.
3.
CLOCK may remain HIGH after latching in data.
4.
DATA is shifted in with the MSB first.
5.
For DATA definitions, refer to Table 2.
Serial Data Input Timing Waveform[2, 3, 4, 5]
Timing Waveforms (continued)
CLOCK
//
LE
//
t2
t1
t3
t4
t5
DATA
PD = MSB
PRE
B1
A7
CNT2
CNT1 = LSB
//
t6
//
Table 1. Control Configuration
CNT1
CNT2
Function
00
Program Reference 2: R = 3 to 32767, set PLL2 (low frequency) phase detector
polarity, set current in PLL2, set PLL2 to Hi-Impedance state, set monitor selector to PLL2.
01
Program Reference 1: R = 3 to 32767, set PLL1 (high frequency) phase detector
polarity, set current in PLL1, set PLL1 to Hi-Impedance state, set monitor selector to PLL1
10
Program Counter for PLL2: A = 0 to 15, B = 3 to 2047, set PLL2 prescaler ratio, set PLL2
to power-down.
11
Program Counter for PLL1: A = 0 to 63, B = 3 to 2047, set PLL1 prescaler ratio, set PLL1
to power-down.
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