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參數(shù)資料
| 型號： | CYW311OXCT |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | LEAD FREE, SSOP-48 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 287K |
| 代理商： | CYW311OXCT |
W311
......................... Document #: 38-07703 Rev. ** Page 2 of 18
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
RST#
CPU1:3
32
39, 38, 35
O
(open
drain)
O
System Reset Output: Open-drain system reset output.
CPU Clock Output: Frequency is set by the FS0:4 input or through serial input
interface. The CPU1:3 outputs are gated by the CLK_STOP# input.
CPU_STOP#
34
I
CPU Output Control: 3.3V LVTTL-compatible input that stop CPU1:3.
PCI1:8
10, 11, 13,
14, 16, 17,
18, 20
O
PCI Clock Outputs 1 through 8: Frequency is set by FS0:4 inputs or through
serial input interface; see Table 5 for details. PCI1:8 outputs are gated by the
PCI_STOP# input.
PCI_STOP#
33
O
PCI_STOP# Input: 3.3V LVTTL-compatible input that stops PCI1:8.
PCI_F
9
O
Free-Running PCI Clock Output: Frequency is set by FS0:4 inputs or through
serial input interface; see Table 5 for details.
FS0:1
AGP0:2
21, 22
23, 26, 27
I
O
Frequency Selection Inputs: Selects CPU clock frequency as shown in Table 1.
AGP Clock Output: This pin serves as the select strap to determine device
operating frequency as described in Table 5.
APIC0:2
48MHz/FS3
45, 44, 42
6
O
I/O
APIC Clock Output: APIC clock outputs.
48 MHz Output/Frequency Select 3: 48 MHz is provided in normal operation.
In standard PC systems, this output can be used as the reference for the Universal
Serial Bus host controller. This pin also serves as a power-on strap option to
determine device operating frequency as described in Table 5.
24_48MHz/
FS2
REF1/FS4
7
47
I/O
24_48 MHz Output/Frequency Select 2: In standard PC systems, this output
can be used as the clock input for a Super I/O chip. The output frequency is
controlled by Configuration Byte 3 bit[6]. The default output frequency is 24 MHz.
This pin also serves as a power-on strap option to determine device operating
frequency as described in Table 5.
Reference Clock Output 1/Frequency Select 4: 3.3V 14.318 MHz output clock.
This pin also serves as a power-on strap option to determine device operating
frequency as described in Table 5.
REF0
48
O
Reference Clock Output 0: 3.3V 14.318 MHz output clock.
SCLK
28
I
Clock pin for SMBus circuitry.
SDATA
29
I/O
Data pin for SMBus circuitry.
X1
3
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318 MHz crystal connection or as an
external reference frequency input.
X2
41
I
Crystal Connection: An input connection for an external 14.318 MHz crystal. If
using an external reference, this pin must be left unconnected.
VDD_REF,
VDD_48MHz,
VDD_PCI,
VDD_AGP,
VDD_CORE
1, 5,15, 24,
31
P
Power Connection: Power supply for core logic, PLL circuitry, PCI outputs,
reference outputs, 48 MHz output, and 24-48 MHz output, connect to 3.3V supply.
VDD_CPU,
VDD_APIC
41, 46, 37
P
Power Connection: Power supply for APIC and CPU output buffers, connect to
2.5V.
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