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參數(shù)資料
| 型號： | d501gv |
| 廠商： | SIEMENS AG |
| 英文描述： | 8-Bit CMOS Microcontroller(8位 CMOS 微控制器) |
| 中文描述： | 8位CMOS微控制器（8位的CMOS微控制器） |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 47K |
| 代理商： | D501GV |
Semiconductor Group
6
3 V Specification / 06.97
C501GV
AC Characteristics
V
CC
= 3.3 V + 0.3V, – 0.6V;
V
SS
= 0 V
, T
A
= 0 C to + 70 C
(
C
L
for port 0, ALE and PSEN outputs = 50 pF;
C
L
for all other outputs = 40 pF)
Program Memory Characteristics
*) Interfacing the C501 microcontrollers to devices with float times up to 75 ns is permissible. This limited bus
contention will not cause any damage to port 0 drivers.
Parameter
Symbol
Limit Values
Unit
12 MHz
Clock
Variable Clock
1/
t
CLCL
= 1 MHz to 12 MHz
min.
2
t
CLCL
– 40
t
CLCL
– 40
t
CLCL
– 53
–
t
CLCL
– 25
3
t
CLCL
– 35
–
min.
max.
max.
ALE pulse width
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ*)
t
PXAV*)
t
AVIV
t
AZPL
127
–
–
ns
Address setup to ALE
43
–
–
ns
Address hold after ALE
30
–
–
4
t
CLCL
– 100
–
ns
ALE low to valid instr in
–
233
ns
ALE to PSEN
58
–
ns
PSEN pulse width
215
–
–
3
t
CLCL
– 100
–
t
CLCL
– 20
–
5
t
CLCL
– 115
–
ns
PSEN to valid instr in
–
150
ns
Input instruction hold after PSEN
0
–
0
ns
Input instruction float after PSEN
–
63
–
t
CLCL
– 8
–
ns
Address valid after PSEN
75
–
ns
Address to valid instr in
–
302
ns
Address float to PSEN
0
–
0
ns
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