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參數(shù)資料
| 型號： | D87C51 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, UVPROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | CERDIP-40 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 284K |
| 代理商： | D87C51 |
87C51/80C51BH/80C31BH
NOTES:
1. ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V
OL
s of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed
0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
3. Capacitive loading on Ports 0 and 2 may cause the V
OH
on ALE and PSEN to momentarily fall below the 0.9V
CC
specifi-
cation when the address bits are stabilizing.
4. See Figures 6 through 8 for I
CC
test conditions. Minimum V
CC
for Power Down is 2V.
5. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
Maximum I
OL
per 8-bit portD
10 mA
Port 0:
26 mA
15 mA
71 mA
Ports 1, 2, and 3:
Maximum total I
for all output pins:
If I
OL
exceeds the test condition, V
OL
may exceed the related specification.
Pins are not guaranteed to sink greater than the listed test conditions.
272335–26
Figure 5. 87C51/BH I
CC
vs Frequency
10
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