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| 型號： | DAC1008D750HN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating |
| 中文描述： | 10-BIT DAC, PQCC64 |
| 封裝： | 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, HVQFN-64 |
| 文件頁數(shù)： | 71/99頁 |
| 文件大?。?/td> | 547K |
| 代理商： | DAC1008D750HN |
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DAC1008D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 5 January 2011
71 of 99
NXP Semiconductors
DAC1008D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
10.15.2.10
Page 5 bit definition detailed description
Please refer to
Table 108
for a register overview and their default values. In the following
tables, all the values emphasized in bold are the default values.
Table 109. ILA_MON_1_0 register (address 00h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 4
ILA_MON_LN1[3:0]
3 to 0
ILA_MON_LN0[3:0]
Access
R
R
Value
-
-
Description
ila_buf_ln1 pointer
ila_buf_ln0 pointer
Table 110. ILA_MON_3_2 register (address 01h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 4
ILA_MON_LN3[3:0]
3 to 0
ILA_MON_LN2[3:0]
Access
R
R
Value
-
-
Description
ila_buf_ln3 pointer
ila_buf_ln2 pointer
Table 111. ILA_BUF_ERR register (address 02h) bit description
Default settings are shown highlighted.
Bit
Symbol
3
ILA_BUF_ERR_LN3
Access
R
Value
Description
lane 3 ila buffer error
ila_buf_ln3 pointer is in range
ila_buf_ln3 pointer is out of range
0
1
2
ILA_BUF_ERR_LN2
R
lane 2 ila buffer error
ila_buf_ln2 pointer is in range
ila_buf_ln2 pointer is out of range
lane 1 ila buffer error
ila_buf_ln1 pointer is in range
ila_buf_ln1 pointer is out of range
lane 0 ila buffer error
ila_buf_ln0 pointer is in range
ila_buf_ln0 pointer is out of range
0
1
1
ILA_BUF_ERR_LN1
R
0
1
0
ILA_BUF_ERR_LN0
R
0
1
Table 112. CA_MON register (address 03h) bit description
Default settings are shown highlighted.
Bit
Symbol
7 to 6
CA_MON_LN3[1:0]
5 to 4
CA_MON_LN2[1:0]
3 to 2
CA_MON_LN1[1:0]
1 to 0
CA_MON_LN0[1:0]
Access
R
R
R
R
Value
-
-
-
-
Description
clock alignment phase monitor lane 3
clock alignment phase monitor lane 2
clock alignment phase monitor lane 1
clock alignment phase monitor lane 0
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PDF描述 |
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| DAC1008D750HN | Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating |
| DAC1208D650HN | Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating |
| DAC1208D650HN | Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1008D750HN/C1,5 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC DL 10BIT DAC 750MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC1008LCN | 制造商:Texas Instruments 功能描述: |
| DAC1008LCN/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter |
| DAC100ACQ3 | 制造商:Analog Devices 功能描述: |
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