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參數(shù)資料
| 型號： | DAC1391X |
| 英文描述： | DAC1391X 2.5V 12BIT 80MSPS DAC|Data Sheet |
| 中文描述： | DAC1391X 2.5V的12位80Msps的發(fā)展援助委員會|數(shù)據(jù)資料 |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 228K |
| 代理商： | DAC1391X |
SEC ASIC
DAC1350X
10BIT 75MSPS Quad DAC
ANALOG
1. ABOUT TESTABILITY
If you want to test it over full specifications via all channel in main chip(that is, when it is used
as
a block of main chip) you must add many pins(for 60pins of digital inputs, 6pins of
analog outputs, etc) at the main chip to test this DAC block. But usually it is nearly impossible
'cause the total number of pins at main chip is limited. So more efficient method for testing
this DAC block is needed. We offer two ways of testing efficiently here as a reference.
But remember this is not the best thing. You can test it by your own testing method.
2. FIRST METHOD OF TESTABILITY
The first way is adding only extra 10PADs for 10bit parallel digital inputs and 3PADs for
channel selecting and path selecting. You can check quad channels one by one, that is you
can test only one channel at one time. Therefore you can test all three channels by turn
but cannot check all channel at one time. And this method needs extra MUX and
switch blocks for testing. Furthermore we can assure all channels by testing only one channel
because all the quad channels have same architecture and share the same analog reference
block(OPAMP, CM, BGR). This characteristic makes it simple to test this DAC block(when it is
embedded in main chip) by adding another 10PADs for parallel digital inputs and 3PADs for
selecting one channel analog switch block of DAC out of three channels.
3. SECOND METHOD OF TESTABILITY
If above extra 13PADs are burden on you, then you can test it by this second method to
reduce the extra PADs for testing. What is different from above method is that this way needs
only 2 extra PADs(one for 1bit serial digital input and the other for clock signal), but you must
insert extra serial to parallel converter block for converting 1bit 10times high speed digital input
to 10bit parallel digital inputs. And this block may need considerable area. And this method also
needs extra 3PADs for channel selecting and path selecting.
4 ANALYSIS
The voltage applied to VREFOUT is measured at IRSET node . And the voltage value
is proportioned to the reference current value of resistor which is connected to
IRSET node. So you can estimate the full scale current value by measuring the
voltage, and check the DC characteristics of the OPAMP. For reference, as
VBIAS voltage applied to VREFOUT pin is given at IRSET node, the current flowing through
RSET resistor(connected to IRSET pin) is given as VREF/RSET.
If the voltage applied to VREFOUT pin is not same with IRSET node, you can say
"This DAC chip does not work properly", because the internal OPAMP block
makes the two node voltage(IRSET pin, VREFOUT pin) equal. And you have to
check the CCOMP node to see the desired voltage on it. If the desired
voltage is not measured, you can check the DAC output by appling a
desired voltage to the CCOMP pin instead of compensation capacitor directly.
If you use internal reference voltage(BGR's output voltage) instead of external
Vbias by setting the BGRSW low, you can check the BGR's output by checking
the VBIAS pin voltage.
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