參數(shù)資料
型號(hào)： DAC2932PFBR
元件分類(lèi)： DAC
英文描述： DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER
中文描述： 雙通道12位40MSPS數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 21/24頁(yè)
文件大?。?/td> 343K
代理商： DAC2932PFBR
SBAS279C AUGUST 2003 REVISED OCTOBER 2004
www.ti.com
21
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. The first four bits are
the address bits to the four V-DACs. The next 12 bits are
the data bits. These are transferred to the DAC register on
the 16th falling edge of the clock (SCLK).
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for
at least 16 falling edges of SCLK and the DAC is updated
on the 16th falling edge. However, if SYNC is brought high
before the 16th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset and the write
sequence is seen as invalid. Neither an update of the DAC
register contents nor a change in the operating mode
occurs, as shown in Figure 39.
POWER-ON RESET
The V-DACs contain a power-on reset circuit that controls
the output voltage during power-up. On power-up, the
DAC register is filled with zeros and the output voltage is
0V; it remains there until a valid write sequence is made to
the DAC. This is useful in applications where it is important
to know the state of the output of the DAC while it is in the
process of powering up.
GROUNDING, DECOUPLING, AND LAYOUT
INFORMATION
Proper grounding and bypassing, short lead length, and
the use of ground planes are particularly important for
high-frequency designs. Multilayer printed circuit boards
(PCBs) are recommended for best performance since they
offer distinct advantages such as minimization of ground
impedance, separation of signal layers by ground layers,
etc.
The DAC2932 uses separate pins for its analog and digital
supply and ground connections. The placement of the
decoupling capacitor should be such that the analog
supply (+V
A
) is bypassed to the analog ground (AGND),
and the digital supply bypassed to the digital ground
(DGND). In most cases, 0.1
μ
F ceramic chip capacitors at
each supply pin are adequate to provide a low impedance
decoupling path. Keep in mind that their effectiveness
largely depends on the proximity to the individual supply
and ground pins. Therefore, they should be located as
close as physically possible to those device leads.
Whenever possible, the capacitors should be located
immediately under each pair of supply/ground pins on the
reverse side of the PCB. This layout approach minimizes
the parasitic inductance of component leads and PCB
runs.
Further supply decoupling with surface-mount tantalum
capacitors (1
μ
F to 4.7
μ
F) can be added as needed in
proximity of the converter.
Low noise is required for all supply and ground
connections to the DAC2932. It is recommended to use a
multilayer PCB with separate power and ground planes.
Mixed signal designs require particular attention to the
routing of the different supply currents and signal traces.
Generally, analog supply and ground planes should only
extend into analog signal areas, such as the DAC output
signal and the reference signal. Digital supply and ground
planes must be confined to areas covering digital circuitry,
including the digital input lines connecting to the converter,
as well as the clock signal. The analog and digital ground
planes should be joined together at one point underneath
the DAC. This can be realized with a short track of
approximately 1/8” (3mm).
The power to the DAC2932 should be provided through
the use of wide PCB runs or planes. Wide runs present a
lower trace impedance, further optimizing the supply
decoupling. The analog and digital supplies for the
converter should only be connected together at the supply
connector of the PCB. In the case of only one supply
voltage being available to power the DAC, ferrite beads
along with bypass capacitors can be used to create an LC
filter. This will generate a low-noise analog supply voltage
that can then be connected to the +V
A
supply pin of the
DAC2932.
While designing the layout, it is important to keep the analog
signal traces separated from any digital line, in order to
prevent noise coupling onto the analog signal path.
CLK
SYNC
DIN
Invalid Write Sequence:
SYNC high before 16th falling edge
Valid Write Sequence:
Output updates on the 16th falling edge
DB15
DB0
DB15
DB0
Figure 39. SYNC Interrupt Facility
相關(guān)PDF資料
PDF描述
DAC2932PFBT DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER
DAC312BR 12-Bit Digital-to-Analog Converter
DAC312GBC 12-Bit Digital-to-Analog Converter
DAC312FR 12-Bit High Speed Multiplying D/A Converter
DAC312HP 12-Bit High Speed Multiplying D/A Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DAC2932PFBRG4 功能描述:數(shù)模轉(zhuǎn)換器- DAC Dual 12-Bit 40MSPS RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC2932PFBT 功能描述:數(shù)模轉(zhuǎn)換器- DAC Dual 12-Bit 40MSPS RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC2932PFBTG4 功能描述:數(shù)模轉(zhuǎn)換器- DAC Dual 12-Bit 40MSPS RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC-2-CG 制造商:Thomas & Betts 功能描述:
DAC2K5G4 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:20-Bit, Low-Power Digital-to-Analog Converter
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