參數(shù)資料
型號: DAC4813
英文描述: QUAD 12-BIT DIGITAL-TO-ANALOG CONVERTER 12-bit port interface
中文描述: 四核12位數(shù)字至模擬轉(zhuǎn)換器12位端口接口
文件頁數(shù): 7/8頁
文件大小: 213K
代理商: DAC4813
DAC4813
7
TYPICAL PERFORMANCE CURVES
(CONT)
T
A
= +25
°
C, V
CC
=
±
15V unless otherwise noted.
DISCUSSION OF
SPECIFICATIONS
LINEARITY ERROR
Linearity error is defined as the deviation of the analog
output from a straight line drawn between the end points
(digital inputs all “1s” and all “0s”). DAC4813 linearity
error is
±
1/2LSB max at +25
o
C.
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error (DLE) is the deviation from a
1LSB output change from one adjacent state to the next. A
DLE specification of 1/2LSB means that the output step size
can range from 1/2LSB to 3/2LSB when the digital input
code changes from one code word to the adjacent code word
If the DLE is more positive than –1LSB, the D/A is said to
be monotonic.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital input values.
DAC4813 is monotonic over their specification temperature
range –40
o
C to +85
o
C.
DRIFT
Gain Drift
is a measure of the change in the Full Scale
Range (FSR) output over the specification temperature range.
Gain Drift is expressed in parts per million per degree
Celsius (ppm/
o
C).
Bipolar Zero Drift
is measured with a data input of 800
.
The D/A is configured for bipolar output. Bipolar Zero Drift
is expressed in parts per million of Full Scale Range per
degree Celsius (ppm of FSR/
o
C).
SETTLING TIME
Settling Time is the total time (including slew time) for the
output to settle to within an error band around its final value
after a change in input. Settling times are specified to
±
0.01% of Full Scale Range (FSR) for two conditions: one
for a FSR output change of 20V (25k
feedback) and one
for a 1LSB change. The 1LSB change is measured at the
Major Carry (7FF
to 800
, and 800
to 7FF
), the
input code transition at which worst-case settling time oc-
curs.
OPERATION
INTERFACE LOGIC
The bus interface logic of the DAC4813 consists of two
independently addressable latches in two ranks for each
D/A converter. The first rank consists of one 12-bit input
latch which can be loaded directly from a 12- or 16-bit
microprocessor/microcontroller bus. The input latch holds
data temporarily before it is loaded into the second latch, the
D/A latch. This double buffered organization permits simul-
taneous update of all D/As.
All latches are level-triggered. Data present when the con-
trol signals are logic “0” will enter the latch. When the
control signals return to logic “1”, the data is latched.
CAUTION:
DAC4813 was designed to use WR as the fast
strobe. WR has a much faster logic path than EN
(or
LDAC). Therefore, if one permanently wires WR to DCOM
and uses only EN
to strobe data into the latches, the DATA
HOLD time will be long, approximately 20ns to 30ns, and
this time will vary considerably in this range from unit to
unit. DATA HOLD time using WR is 5ns max.
20
10
0
–10
–20
–40
O
–2
Time (μs)
SETTLING TIME, –10V TO +10V
+5
0
W
0
2
4
6
8
10
12
14
V
OUT
WR
V
OUT
1LSB = 4.88mV
20
10
0
–10
–20
O
–2
Time (μs)
SETTLING TIME, +10V TO –10V
+5
0
0
2
4
6
8
10
12
W
1LSB = 4.88mV
V
OUT
WR
V
OUT
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DAC4814AP 制造商:BB 制造商全稱:BB 功能描述:Quad 12-Bit Digital-to-Analog Converter Serial Interface
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