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參數(shù)資料
| 型號： | DAC4815BP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 151K |
| 代理商： | DAC4815BP |
8
DAC4815
D11
(MSB)
D10
D9
D0
(LSB)
AGND
I
RR
R
2R
R
OUT
V
REF
R
FB
DIGITAL-TO-ANALOG GLITCH
Ideally, the DAC output would make a clean step change in
response to an input code change. In reality, glitches occur
during the transition. See Typical Performance Curves.
DIGITAL CROSSTALK
Digital crosstalk is the glitch impulse measured at the output
of one DAC due to a full scale transition on the other
DAC—see Typical Performance Curves. It is dominated by
digital coupling. Also, the integrated area of the glitch pulse
is specified in nV–s. See table of electrical specifications.
DIGITAL FEEDTHROUGH
Digital feedthrough is the noise at a DAC output due to
activity on the digital inputs—see Typical Performance
Curves.
OPERATION
Depending on the address selected, the 4 MSBs or the 8
LSBs are written into the appropriate input register for each
DAC when the WR signal is brought low. The data are
latched in the input register when the WR goes high. Data
are then transferred from the input registers to the DAC latch
registers by bringing LE low. The data are latched in the
DAC latch registers when LE goes high. All DACs are
updated simultaneously.
When CLR is brought low, the input registers are cleared to
000HEX while the DAC registers = 800HEX. If LE is brought
low after CLR the DACs are updated with 000
HEX resulting
in –10V (bipolar) or OV (unipolar) on the output.
CIRCUIT DESCRIPTION
Each of the four DACs in the DAC4815 consists of a CMOS
logic section, a CMOS DAC cell, and an output amplifier.
One buried-zener +10.0V reference and a –10V reference
are shared by all DACs.
Figure 1 is a simplified circuit for a DAC cell. An R, 2R
ladder network is driven by a voltage reference at V
REF.
Current from the ladder is switched either to IOUT or AGND
by 12 single-pole double-throw CMOS switches. This main-
tains constant current in each leg of the ladder regardless of
digital input code. This makes the resistance at V
REF con-
stant (it can be driven by either a voltage or current refer-
ence). The reference can be either positive or negative
polarity with a range of up to
±10V.
CMOS switches included in series with the ladder terminat-
ing resistor and the feedback resistor, RFB, compensate for
the temperature drift of the ladder switch ON resistance.
The output op amps are connected as transimpedance ampli-
fiers to convert the DAC-cell output current into an output
voltage. They have been specially designed and compen-
sated for precision and fast settling in this application.
POWER SUPPLY CONNECTIONS
The DAC4815 is specified for operation with power sup-
plies of VL = +5V and VS = either ±12V or ±15V. Even with
the V
S supplies at ±11.4V the DACs can swing a full ±10V.
Power supply decoupling capacitors (1
F tantalum) should
be located close to the DAC power supply connections.
Separate digital and analog ground pins are provided to
permit separate current returns. They should be connected
together at one point. Proper layout of the two current
returns will prevent digital logic switching currents from
degrading the analog output signal. The analog ground
current is code dependent so the impedance to the system
reference ground must be kept to a minimum. Connect
DACs as shown in Figure 2 or use a ground plane to keep
ground impedance less than 0.1
for less than 0.1LSB error.
±10V OUTPUT RANGE CONNECTION
For a
±10V bipolar output connect the DAC4815 as shown
in Figure 3.
CONNECTION TO DIGITAL BUS
DAC4815s can easily be connected to a
processor bus.
Decode your address lines to derive the control signals
shown in Figure 4. Only one LATCH signal is required for
a system where all DAC4815s are updated simultaneously.
If your want to update DAC4815s independently, use sepa-
rate LATCH signals. The LATCH and WRITE signals can
be brought low simultaneously to update the DAC registers
with the same processor instruction that writes the final 8-bit
data word the DAC input registers.
FIGURE 1. Simplified Circuit Diagram of DAC Cell.
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