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參數(shù)資料
| 型號： | DAC600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-Bit 256MHz Monolithic Dightal-To-Analog Converter(12位 256MHz單片D/A轉(zhuǎn)換器) |
| 中文描述： | 12位256MHz單片Dightal到模擬轉(zhuǎn)換器（12位256MHz單片的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 198K |
| 代理商： | DAC600 |
DAC600
9
Decoding of bits 1-4 into 15 segments and synchronizing the
data with a master/slave register reduces glitching. If the
BYPASS input is low, data is transferred to the output on the
positive going edge of the clock. If BYPASS is high, data is
transferred to the output regardless of clock state. All digital
inputs are ECL compatible.
The output current sees 50
of output impedance from the
equivalent resistance of a R-2R ladder. With all of the
current sources off, the output voltage is at 0V. With all
current sources on (–20mA), the output voltage is at –1V.
Transfer function information is given in Tables I and II.
THEORY OF OPERATION
The DAC600 employs a familiar architecture where input
bits switch on the appropriate current sources (Figure 1.)
Bits 1-4 are decoded into 15 segments after the first set of
latches. The edge triggered master-slave latches are driven
by an internal clock buffer. Current sources for bits 5 and 6
are scaled down in binary fashion. These current sources are
switched directly to the output of the R-2R ladder. Bits 7-12
are properly scaled and fed to the laser trimmed R-2R
ladder.
Current
Sources
Current
Switches
50
50
(Ladder
Equivalent
Resistance)
V
OUT
V
OUT NOT
L
L
MSB
2
3
4
5
6
7
8
9
10
11
LSB
Clock Buffer
CLK
CLK
R
OFFSET
V
REF
LGND
Bypass
Decoder
FIGURE 1. Basic DAC600 Architecture.
BIT
VOLTAGE (No External Load, V
OUT
)
–0.5
–0.25
–0.125
–62.5mV
–31.25mV
–15.625mV
–7.8125mV
–3.9063mV
–1.9531mV
–976
μ
V
–488
μ
V
–244
μ
V
1
2
3
4
5
6
7
8
9
10
11
12 (LSB)
TABLE II. Nominal Bit Weight Values.
INPUT BITS OUTPUT VOLTAGES
1 2 3 4 5 6 7 8 9 10 11 12
V
OUT
NV
OUT
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0
0
0
0
0
1
0V
–0.999756V
0.999512V
–244
μ
V
1 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0
1
0
1
0
1
–0.5
–0.499756
0
–0.999756V
TABLE I. Input Code vs Output Voltage Relationships.
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