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參數(shù)資料
| 型號： | DAC7541AKPG4 |
| 英文描述： | Low Cost 12-Bit CMOS Four-Quadrant Multiplying DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 低成本12位CMOS四象限乘法數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 157K |
| 代理商： | DAC7541AKPG4 |
6
DAC7541A
FIGURE 2. DAC7541A Equivalent Circuit (All inputs
LOW).
FIGURE 3. DAC7541A Equivalent Circuit (All inputs
HIGH).
1/4096
I
L
90pF
I
L
60pF
R = 10k
R
FB
I
OUT 1
I
OUT 2
I
REF
V
REF
R
≈
10k
1/4096
I
L
90pF
I
L
55pF
R = 10k
R
FB
I
OUT 2
I
OUT 1
R
≈
10k
I
REF
V
REF
amplifier, board layout, and power supply decoupling will
all affect the dynamic performance of the DAC7541A. The
use of a compensation capacitor may be required when high-
speed operational amplifiers are used. It may be connected
across the amplifier’s feedback resistor to provide the nec-
essary phase compensation to critically dampen the output.
See Figures 4 and 6.
APPLICATIONS
OP AMP CONSIDERATIONS
The input bias current of the op amp flows through the
feedback resistor, creating an error voltage at the output of
the op amp. This will show up as an offset through all codes
of the transfer characteristics. A low bias current op amp
such as the OPA606 is recommended.
Low offset voltage and V
OS
drift are also important. The
output impedance of the DAC is modulated with the digital
code. This impedance change (approximately 10k
to 30k
)
is a change in closed-loop gain to the op amp. The result is
that V
OS
will be multiplied by a factor of one to two
depending on the code. This shows up as a linearity error.
Offset can be adjusted out using Figure 4. Gain may be
adjusted using Figure 5.
UNIPOLAR BINARY OPERATION
(Two-Quadrant Multiplication)
Figure 4 shows the analog circuit connections required for
unipolar binary (two-quadrant multiplication) operation. With
a DC reference voltage or current (positive or negative
polarity) applied at pin 17, the circuit is a unipolar D/A
converter. With an AC reference voltage or current, the
circuit provides two-quadrant multiplication (digitally con-
trolled attenuation). The input/output relationship is shown
in Table I.
BINARY INPUT
ANALOG OUTPUT
MSB
LSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
–V
REF
(4095/4096)
–V
REF
(2048/4096)
–V
REF
(1/4096)
0V
TABLE I. Unipolar Codes.
C
1
phase compensation (10 to 25pF) in Figure 4 may be
required for stability when using high speed amplifiers. C
1
is used to cancel the pole formed by the DAC internal
feedback resistance and output capacitance at Out
1
.
R
1
in Figure 5 provides full scale trim capability—load the
DAC register to 1111 1111 1111, adjust R
1
for V
OUT
= –
V
REF
(4095/4096). Alternatively, full scale can be adjusted
by omitting R
1
and R
2
and trimming the reference voltage
magnitude.
BIPOLAR FOUR-QUADRANT OPERATION
Figure 6 shows the connections for bipolar four-quadrant
operation. Offset can be adjusted with the A
1
to A
2
summing
resistor, with the input code set to 1000 0000 0000. Gain
may be adjusted by varying the feedback resistor of A
2
. The
input/output relationship is shown in Table II.
BINARY INPUT
ANALOG OUTPUT
MSB
LSB
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
+V
REF
(2047/2048)
0V
–V
REF
(1/2048)
–V
REF
(2048/2048)
TABLE II. Bipolar Codes.
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