參數(shù)資料
型號: DAC7614EB
英文描述: Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER
中文描述: 四,串行輸入,12位電壓輸出數(shù)字模擬轉換器
文件頁數(shù): 10/12頁
文件大?。?/td> 483K
代理商: DAC7614EB
10
DAC7614
REFERENCE INPUTS
The reference inputs, V
REFL
and V
REFH
, can be any voltage
between V
SS
+ 2.25V and V
DD
– 2.25V provided that
V
REFH
is at least 1.25V greater than V
REFL
. The minimum
output of each DAC is equal to V
REFL
– 1LSB plus a small
offset voltage (essentially, the offset of the output op amp).
The maximum output is equal to V
REFH
plus a similar
offset voltage. Note that V
SS
(the negative power supply)
must either be connected to ground or must be in the range
of –4.75V to –5.25V. The voltage on V
SS
sets several bias
points within the converter. If V
SS
is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not guaranteed.
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 0.6 milliamp. Bypassing the reference volt-
age or voltages with a 0.1
μ
F capacitor placed as close as
possible to the DAC7614 package is strongly recommended.
DIGITAL INTERFACE
Figure 3 and Table I provide the basic timing for the
DAC7614. The interface consists of a serial clock (CLK),
serial data (SDI), and a load DAC signal (LOADDACS). In
addition, a chip select (CS) input is available to enable serial
communication when there are multiple serial devices. An
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
DS
Data Valid to CLK Rising
25
ns
t
DH
Data Held Valid after CLK Rises
20
ns
t
CH
CLK HIGH
30
ns
t
CL
CLK LOW
50
ns
t
CSS
CS LOW to CLK Rising
55
ns
t
CSH
CLK HIGH to CS Rising
15
ns
t
LD1
LOADDACS HIGH to CLK Rising
40
ns
t
LD2
CLK Rising to LOADDACS LOW
15
ns
t
LDDW
LOADDACS LOW Time
45
ns
t
RSSH
RESETSEL Valid to RESET LOW
25
ns
t
RSTW
RESET LOW Time
70
ns
t
S
Settling Time
10
μ
s
FIGURE 3. DAC7614 Timing.
TABLE I. Timing Specifications (T
A
= –40
°
C to +85
°
C).
asynchronous reset input (RESET) is provided to simplify
start-up conditions, periodic resets, or emergency resets to a
known state.
The DAC code and address are provided via a 16-bit serial
interface as shown in Figure 3. The first two bits select the
DAC register that will be updated when LOADDACS goes
LOW (see Table II). The next two bits are not used. The last
12 bits is the DAC code which is provided, most significant
bit first.
A1
(MSB)
(LSB)
SDI
CLK
CS
LOADDAC
A0
X
X
D11
D10
D9
D3
D2
D1
D0
SDI
CLK
LOADDAC
RESET
V
OUT
tcss
t
LD1
t
CL
t
CH
t
DS
t
DH
t
LD2
t
LDDW
t
LDDW
t
S
t
RSTW
t
RSSH
t
CSH
t
S
1 LSB
ERROR BAND
1 LSB
ERROR BAND
RESETSEL
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