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參數(shù)資料
| 型號： | DAC7664YBR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16-BIT, QUAD VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 16位四路電壓輸出數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大小： | 452K |
| 代理商： | DAC7664YBR |
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SBAS271 MARCH 2004
www.ti.com
22
ANALOG OUTPUTS
When V
SS
= –5V (dual-supply operation), the output
amplifier can swing to within 2.25V of the supply rails over
a range of –40
°
C to +85
°
C. When V
SS
= 0V (single-supply
operation), and with R
LOAD
also connected to ground, the
output can swing to within 5mV of ground. Care must be
taken when measuring the zero-scale error when
V
SS
= 0V. Since the output voltage cannot swing below
ground, the output voltage may not change for the first few
digital input codes (0000h, 0001h, 0002h, etc.) if the output
amplifier has a negative offset.
Due to the high accuracy of these DACs, system design
problems such as grounding and contact resistance are
very important. A 16-bit converter with a 2.5V full-scale
range has a 1LSB value of 38
μ
V. With a load current of
1mA, series wiring and connector resistance of only 40m
(R
W2
) will cause a voltage drop of 40
μ
V, as shown in
Figure 56. To understand what this means in terms of
system layout, the resistivity of a typical 1-ounce
copper-clad printed circuit board is 1/2 m
per square. For
a 1mA load, a 0.01-inch-wide printed circuit conductor 0.6
inches long will result in a voltage drop of 30
μ
V.
The DAC7664 offers a force and sense output
configuration for the high open-loop gain output amplifier.
This feature allows the loop around the output amplifier to
be closed at the load (as shown in Figure 56), thus
ensuring an accurate output voltage.
DIGITAL INTERFACE
Table 1 shows the basic control logic for the DAC7664.
Note that each internal register is edge-triggered and not
level-triggered. When the LDAC signal is transitioned to
high, the digital word currently in the register is latched.
The first set of registers (the input registers) are triggered
via the A0, A1, R/W, and CS inputs. Only one of these
registers is transparent at any given time.
The double-buffered architecture is designed mainly so
each DAC input register can be written to at any time and
then all DAC voltages updated simultaneously by the
rising edge of LDAC. It also allows a DAC input register to
be written to at any point and the DAC voltages to be
synchronously changed via a trigger signal connected to
LDAC.
V
OUT
A Sense1
V
OUT
A
AGND
V
OUT
B Sense1
V
OUT
B
6
5
8
59
58
DAC7664
R
W1
R
W2
V
OUT
R
W1
R
W2
V
OUT
Figure 56. Analog Output Closed-Loop Configuration (1/2 DAC7664). R
W
represents wiring resistances.
Table 1. DAC7664 Logic Truth Table
A1
L
L
H
H
L
L
H
H
X
X
X
X
A0
L
H
L
H
L
H
L
H
X
X
X
X
R/W
L
L
L
L
H
H
H
H
X
X
X
X
CS
L
L
L
L
L
L
L
L
H
H
X
X
RST
H
H
H
H
H
H
H
H
H
H
↑
↑
RSTSEL
X
X
X
X
X
X
X
X
X
X
L
H
LDAC
X
X
X
X
X
X
X
X
↑
H
X
X
INPUT REGISTER
Write
Write
Write
Write
Read
Read
Read
Read
Hold
Hold
Reset to zero
Reset to mid-scale
DAC REGISTER
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Write
Hold
Reset to zero
Reset to mid-scale
MODE
Write input
Write input
Write input
Write input
Read input
Read input
Read input
Read input
Update
Hold
Reset to zero
Reset to mid-scale
DAC
A
B
C
D
A
B
C
D
All
All
All
All
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