參數(shù)資料
型號: DAC7724N
元件分類: 外設(shè)及接口
英文描述: Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C
中文描述: 電可擦除可編程邏輯器件
文件頁數(shù): 13/15頁
文件大小: 451K
代理商: DAC7724N
13
DAC7724, 7725
ANALOG OUTPUTS
When V
SS
= –15V (dual supply operation), the output
amplifier can swing to within 4V of the supply rails, guar-
anteed over the –40
°
C to +85
°
C temperature range. With
V
SS
= 0V (single-supply operation) and R
LOAD
connected to
ground, the output can swing to ground. Note that the
settling time of the output op-amp will be longer with
voltages very near ground. Additionally, care must be taken
when measuring the zero-scale error when V
SS
= 0V. Since
the output voltage cannot swing below ground, the output
voltage may not change for the first few digital input codes
(000
H
, 001
H
, 002
H
, etc.) if the output amplifier has a nega-
tive offset. At the negative offset limit of –4 LSB (-9.76mV),
for the single-supply case, the first specified output starts at
code 004
H
.
REFERENCE INPUTS
For dual-supply operation, the reference inputs, V
REFL
and
V
REFH
, can be any voltage between V
SS
+ 4V and V
CC
– 4V
provided that V
REFH
is at least 1.25V greater than V
REFL
.
For single-supply operation (V
SS
= 0V), V
REFL
value can be
above 0V, with the same provision that V
REFH
is at least
1.25V greater than V
REFL
. The minimum output of each
DAC is equal to V
REFL
plus a small offset voltage (essen-
tially, the offset of the output op-amp). The maximum
output is equal to V
REFH
plus a similar offset voltage. Note
that V
SS
(the negative power supply) must either be con-
nected to ground or must be in the range of –14.25V to
–15.75V. The voltage on V
SS
sets several bias points within
the converter, if V
SS
is not in one of these two configura-
tions, the bias values may be in error and proper operation
of the device is not guaranteed.
The current into the V
REF
H input and out of V
REF
L depends
on the DAC output voltages and can vary from a few
microamps to approximately 0.3mA. The reference input
appears as a varying load to the reference. If the reference
can sink or source the required current, a reference buffer is
not required. See “Reference Current vs Code” in the Typi-
cal Performance Curves.
The analog supplies (or the analog supplies and the refer-
ence power supplies) have to come up first. If the power
supplies for the references come up first, then the V
CC
and
V
SS
supplies will be “powered from the reference via the
ESD protection diodes” (see page 4).
Bypassing the reference voltage or voltages with at least a
0.1uF capacitor placed as close to the DAC7724/25 package
is strongly recommended.
FIGURE 3. Basic Dual-Supply Operation of the DAC7724/25.
1
2
3
4
V
REFH
V
OUTB
Load DAC Registers
Reset DACs
(1)
V
OUTA
V
SS
5
GND
6
RESET
7
8
9
10
11
12
13
14
LDAC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
V
REFL
V
OUTC
DAC7724
DAC7725
V
OUTD
V
CC
28
27
26
25
V
DD
24
CS
23
A0
A1
R/W
DB11
DB10
DB9
DB8
DB7
22
21
20
19
18
17
16
15
Chip Select
–10V to +10V
–10V to +10V
Read/Write
Data Bus
Address Bus
or Decoder
NOTE: (1) Reset LOW sets all DACs to code 800
H
on the DAC7724 and to code 000
H
on the DAC7725.
–10.000V
0.1
μ
F
–10V to +10V
–10V to +10V
–15V
+10.000V
0.1
μ
F
0.1
μ
F
1
μ
F to 10
μ
F
+
Data Bus
+15V
0.1
μ
F
1
μ
F to 10
μ
F
+
+5V
0.1
μ
F
1
μ
F to 10
μ
F
+
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