參數(shù)資料
型號: DAC7725U/1K
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO28
封裝: GREEN, SOIC-28
文件頁數(shù): 7/16頁
文件大?。?/td> 460K
代理商: DAC7725U/1K
15
DAC7724, 7725
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tRCS
CS LOW for Read
200
ns
tRDS
R/W HIGH to CS LOW
10
ns
tRDH
R/W HIGH after CS HIGH
10
ns
tDZ
CS HIGH to Data Bus in High Impedance
100
ns
tCSD
CS LOW to Data Bus Valid
100
160
ns
tWCS
CS LOW for Write
50
ns
tWS
R/W LOW to CS LOW
0
ns
tWH
R/W LOW after CS HIGH
0
ns
tAS
Address Valid to CS LOW
0
ns
tAH
Address Valid after CS HIGH
0
ns
tLD
LDAC Delay from CS HIGH
10
ns
tDS
Data Valid to CS LOW
0
ns
tDH
Data Valid after CS HIGH
0
ns
tLWD
LDAC LOW
50
ns
tRESET
RESET LOW Time
50
ns
tS
Settling Time
10
s
TABLE II. Timing Specifications (TA = –40°C to +85°C).
FIGURE 4. Digital Input and Output Timing.
t
RCS
CS
t
RDS
t
RDH
t
AS
t
CSD
t
DZ
t
AH
R/W
A0/A1
Data Out
Data Valid
Data Read Timing
±0.012% of FSR
Error Band
±0.012% of FSR
Error Band
Mid-Scale
RESET
V
OUT, DAC7725
+FS
–FS
V
OUT, DAC7724
+FS
–FS
DAC7724/25 Reset Timing
t
RESET
t
S
t
WCS
CS
t
WS
t
AS
t
AH
t
WH
R/W
A0/A1
t
S
±0.012% of FSR
Error Band
±0.012% of FSR
Error Band
LDAC
t
DS
t
DH
Data In
V
OUT
Data Write Timing
t
LWD
t
LD
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