參數(shù)資料
型號： DAC7731E1K
英文描述： 16-Bit, Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
中文描述： 16位，電壓輸出，串行輸入數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù)： 14/19頁
文件大?。?/td> 360K
代理商： DAC7731E1K
DAC7731
SBAS249
14
www.ti.com
REFERENCE
CONFIGURATION
CONFIGURATION R
OFFSET
Internal
0V to +10V
Reference
–
10V to +10V
–
5V to +5V
OUTPUT
PIN STRAPPING
RFB1
V
SJ(1)
RFB2
to V
REF
NC
to AGND to V
OUT
to V
OUT
+1.666V
to V
REF
to V
OUT
to V
OUT
NC
NC
to AGND to V
OUT
to V
OUT
to V
OUT
to V
OUT
NC
+5V
to V
OUT
+3.333V
External
Reference
0V to V
REF
–
V
REF
to V
REF
–
V
REF
/2 to V
REF
/2
V
REF
/2
V
REF
/3
V
REF
/6
to V
OUT
NOTE: (1) Voltage measured at V
SJ
for a given configuration.
TABLE IV. Nominal V
SJ
versus V
OUT
and Reference Configu-
ration.
APPLICATIONS
GAIN AND OFFSET CALIBRATION
The architecture of the DAC7731 is designed in such a way
as to allow for easily configurable offset and gain calibration
using a minimum of external components. The DAC7731
has built-in feedback resistors and output amplifier summing
points brought out of the package in order to make the
absolute calibration possible. Figures 9 and 10 illustrate the
relationship of offset and gain adjustments for the DAC7731
in a unipolar configuration and in a bipolar configuration,
respectively.
should be at +10V
–
1LSB for the 0V to +10V or
±
10V output
range and +5V
–
1LSB for the
±
5V output range. Figure 11
shows the generalized external offset and gain adjustment
circuitry using potentiometers.
FIGURE 9. Relationship of Offset and Gain Adjustments for
V
OUT
= 0V to +10V Output Configuration.
Digital Input
H
Input =
FFFF
H
Input =
0000
Gain Adjust
Rotates
the Line
1LSB
+ Full Scale
F
A
(+V
REF
)
Zero Scale
(AGND)
Offset Adjust Translates the Line
FIGURE 10. Relationship of Offset and Gain Adjustments for
V
OUT
=
–
10V to +10V Output Configuration. (Same
Theory Applies for V
OUT
=
–
5V to +5V.)
Digital Input
Input =
0000
H
Gain
Adjust
Rotates
the Line
1LSB
F
R
+ Full
Scale
–
Full-Scale
(
–
V
REF
OR
–
V
REF
/2)
Offset
Adjust
Translates
the Line
H
Input =
FFFF
Input = 8000
H
A
(+V
REF
or +V
REF
/2)
When calibrating the DAC
’
s output, offset should be adjusted
first to avoid first order interaction of adjustments. In unipolar
mode, the DAC7731
’
s offset is adjusted from code 0000
H
and for either bipolar mode, offset adjustments are made at
code 8000
H
. Gain adjustment can then be made at code
FFFF
H
for each configuration, where the output of the DAC
FIGURE 11. Generalized External Calibration Circuitry for
Gain and Symmetrical Offset Adjustment.
R
V
R
R
O
A
R
R
S
4
5
6
7
8
9
1
DAC7731
Optional Gain
Adjust
Optional Offset
Adjust
R
1
R
POT2
R
POT1
R
S
V
OADJ
(Other Connections Omitted
for Clarity)
+
I
SJ
OFFSET ADJUSTMENT
Offset adjustment is accomplished by introducing a small
current into the summing junction (SJ) of the DAC7731. The
voltage at SJ, or V
SJ
, is dependent on the output configura-
tion of the DAC7731. See Table IV for the required pin
strapping for a given configuration and the nominal values of
V
SJ
for each output range.
The current level required to adjust the DAC7731
’
s offset can
be created by using a potentiometer divider as shown in
Figure 11 Another alternative is to use a unipolar DAC in order
to apply a voltage, V
OADJ
, to the resistor R
S
. A
±
2uA current
range applied to SJ will ensure offset adjustment coverage of
the
±
0.1% maximum offset specification of the DAC7731.
When in a unipolar configuration (V
SJ
= 5V), only a single
resistor, R
S
, is needed for symmetrical offset adjustment with
a 0V to 10V V
OADJ
range. When in one of the two bipolar
configurations, V
SJ
is either +3.333V (
±
10V range) or +1.666V
(
±
5V range), and circuit values chosen to match those given
in Table V will provide symmetrical offset adjust. Please refer
to Figure 11 for component configuration.
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