參數(shù)資料
型號: DAC7731EB
英文描述: 16-Bit, Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
中文描述: 16位,電壓輸出,串行輸入數(shù)字到模擬轉換器
文件頁數(shù): 12/19頁
文件大小: 360K
代理商: DAC7731EB
DAC7731
SBAS249
12
www.ti.com
on LDAC is completely asynchronous to the serial interface of
the device and can occur at any time. Care must be taken to
ensure that the entire 16 bits of data are loaded into the input
register before issuing a LDAC active edge. Additional load
commands will have no effect on the DAC output if the data in
the input register is unchanged between rising LDAC edges.
When CS is returned HIGH, the rising edge on CS must
occur when SCLK is HIGH. Application of a rising CS edge
when SCLK is LOW will cause one additional shift in the
serial input shift register, corrupting the desired input data.
TIMING CONSIDERATIONS
The flexible interface of the DAC7731 can operate under a
number of different scenarios as is required by a host
controller. Critical timing for a 16-bit data transfer cycle is
shown in the Interface Timing section of the Timing Charac-
teristics. While this is the most common method of writing to
the DAC7731, the device accepts two additional modes of
data transfer from the host. These are byte transfer mode
and continuous transfer mode.
Byte transfer mode is especially useful when an 8-bit host is
communicating with the DAC. Data transfer can occur with-
out requiring an additional general purpose I/O pin to control
the CS input of the DAC in cycles of 16 clocks. A HIGH state
on CS stops data from coming into and out of the internal
shift register. This provides byte-wide support for 8-bit host
processors. Figure 5 is an example of the timing cycle of
such a data transfer.
The remaining data transfer mode accepted by the DAC7731
is continuous transfer. The CS of the DAC7731 can be tied
LOW or held LOW by the controller for an indefinite number of
serial clock cycles. Each clock cycle will transfer data into the
DAC via SDI and out of the DAC on SDO. Care must be taken
that the LDAC signal to the DAC(s) is timed correctly so that
valid data is transferred into the DAC register on each rising
LDAC edge. ("Valid data" refers to the serial data latched on
each of the 16 rising SCLK edges prior to the occurrence of a
rising LDAC signal.) The rising edge of LDAC must occur
before the first rising SCLK edge of the following 16-bit
transfer. Figure 6 shows continuous transfer timing.
16-Bit Data Word
Most Significant Byte
Least Significant Byte
Byte 1, Word N
Byte 2, Word N
Byte 1, Word N
1
Byte 2, Word N
1
B15
A15
A14
A13
A8
A7
A6
A0
B14
B13
B8
B7
B6
B0
1
2
8
9
10
16
CS
SCLK
SDI
SDO
LDAC
1
2
16
1
2
16
1
2
B15
B14
B1
B0
C15
C14
C1
C0
D15
D14
C14
C15
B0
B1
B14
B15
A0
A1
A14
A15
Word N
Word N + 1
Word N + 2
Word N
1
Word N
Word N + 1
CS
SCLK
SDI
SDO
LDAC
FIGURE 6. Continuous Transfer Control.
FIGURE 5. Byte-Wide Data Write Cycle.
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