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參數(shù)資料
| 型號： | DAC7731EC |
| 英文描述： | 16-Bit, Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 16位，電壓輸出，串行輸入數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 360K |
| 代理商： | DAC7731EC |
DAC7731
SBAS249
13
www.ti.com
V
CC
REF
OUT
REF
IN
REFADJ
V
REF
R
OFFSET
AGND
RFB2
RFB1
SJ
V
OUT
V
DD
V
SS
REFEN
RSTSEL
SCLK
CS
SDO
SDI
LDAC
RST
NC
TEST
DGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DAC7731
V
CC
REF
OUT
REF
IN
REFADJ
V
REF
R
OFFSET
AGND
RFB2
RFB1
SJ
V
OUT
V
DD
V
SS
REFEN
RSTSEL
SCLK
CS
SDO
SDI
LDAC
RST
NC
TEST
DGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DAC7731
From Host
Controller
To next
DAC7731
First Device in Chain
Second Device in Chain
FIGURE 7. DAC7731 Daisy-Chain Schematic.
DAC7731
’
s in a daisy-chained configuration, as shown in
Figure 7.
DAC RESET
The RST and RSTSEL inputs control the reset of the analog
output. The reset command is level triggered by a low signal on
RST. Once RST is LOW, the DAC output will begin settling to
the mid-scale or min-scale code depending on the state of the
RSTSEL input. A HIGH value on RSTSEL will cause V
OUT
to
reset to the mid-scale code (8000
H
) and a LOW value will reset
V
OUT
to min-scale (8000
H
). A change in the state of the RSTSEL
input while RST is LOW will cause a corresponding change in
the reset command selected internally and consequently change
the output value of V
OUT
of the DAC. Note that a valid reset
signal also resets the input register of the DAC to the value
specified by the state of RSTSEL.
SCLK
CS
LDAC
SDI
A15
A14
A0
X
X
X
SDO
1
2
1
2
16
16
LSBs latched
LSBs latched
Both DAC V
OUT
's
are updated
First Data Transfer Cycle
Previous cycle word from host
(to DAC7731 B SDI)
B15
B14
B1
B0
A15
A14
A1
A0
FIGURE 8. DAC7731 Daisy-Chain Timing for Figure 7.
DAISY-CHAINING USING SDO
Multiple DAC7731
’
s can be connected to a single serial port
by attaching each of their control inputs in parallel and daisy-
chaining the SDO and SDI I/O's of each device. The SDO
output of the DAC7731 is active when CS is LOW and can
be left unconnected when not required for use in a daisy-
chain configuration.
Once a data transfer cycle begins, new data is shifted into SDI
and data currently residing in the shift register (from previous
cycle, power-up, or reset command) is presented on SDO, MSB
first. One data transfer cycle for each DAC7731 is required to
update all devices in the chain. The first data cycle written into
the chain will arrive at the last DAC7731 on the final cycle of the
data transfer. Upon completion of the required number of data
transfer cycles (one cycle per device), each DAC voltage output
is updated with a rising edge on the LDAC inputs.
Figure 8 shows the required timing to properly update two
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC7731EC | 制造商:Texas Instruments 功能描述:IC 16BIT DAC SMD 7731 SSOP24 |
| DAC7731EC/1K | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit Sng Ch W/Int +10V Ref & Ser I/F RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7731EC/1KG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit Sng Ch W/Int +10V Ref & Ser I/F RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7731EC1K | 制造商:BB 制造商全稱:BB 功能描述:16-Bit, Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER |
| DAC7731ECG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit Sng Ch W/Int +10V Ref & Ser I/F RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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