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參數(shù)資料
| 型號(hào)： | DAC7734EB |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
| 中文描述： | 單電源RS232C接口線路驅(qū)動(dòng)器/接收器（單電源RS232C接口線收發(fā)器（2發(fā)2收）） |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 1309K |
| 代理商： | DAC7734EB |
21
DAC7734
INPUT
REGISTER
DAC
A1
A0
CS
RST
RSTSEL
LDAC
LOAD
REGISTER
MODE
DAC
L
L
H
H
X
X
X
X
L
H
L
H
X
X
X
X
L
L
L
L
H
H
X
X
H
H
H
H
H
H
↑
↑
X
X
X
X
X
X
L
H
X
X
X
X
↑
H
X
X
L
L
L
L
H
H
X
X
Write
Write
Write
Write
Hold
Hold
Hold
Hold
Hold
Hold
Write
Hold
Write Input
Write Input
Write Input
Write Input
Update
Hold
Reset to Zero
Reset to Midscale
A
B
C
D
All
All
All
All
Reset to Zero
Reset to Midscale
Reset to Zero
Reset to Midscale
TABLE I. DAC7734 Logic Truth Table.
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7734. The
interface consists of a Signal Data Clock (CLK) input, Serial
Data (SDI), DAC Input Register Load Control Signal
(LOAD), and DAC Register Load Control Signal (LDAC).
In addition, a Chip Select (CS) input is available to enable
serial communication when there are multiple serial devices.
An asynchronous Reset (RST) input, by the rising edge, is
provided to simplify start-up conditions, periodic resets, or
emergency resets to a known state, depending on the status
of the reset select (RSTSEL) signal.
The DAC code, quick load control, and address are provided
via a 24-bit serial interface (see Table I). The first two bits
shifted into the shift register, B23 and B22, are the DAC
register address. These bits select the input register that will
be updated when LOAD goes LOW. The third bit, B21, is a
“Quick Load” bit such that if HIGH, the code in the shift
register is loaded into ALL DAC input registers when the
LOAD signal goes LOW, independent of the state of the
address bits, B23 and B22. If the “Quick Load” bit is LOW,
the contents of the shift register is loaded only to the DAC
register that is addressed. Bits B20 through B16 are not used
and can assume any logical value. The last sixteen bits, B15
through B0, make up the DAC code to be loaded into the
selected input register.
The internal DAC register is edge triggered and not level
triggered. When the LDAC signal is transitioned from LOW
to HIGH, the digital word currently in the DAC input
register is latched. The first set of registers (the DAC input
registers) are level triggered via the LOAD signal. This
double-buffered architecture has been designed so that new
data can be entered for each DAC without disturbing the
analog outputs. When the new data has been entered into the
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
A1
A0
X
X
X
X
X
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
QUICK
LOAD
SERIAL DATA INPUT
device, all of the DAC outputs can be updated simulta-
neously by the rising edge of LDAC. Additionally, it allows
the DAC input registers to be written to at any point, then the
DAC output voltages can be synchronously changed via a
trigger signal (LDAC).
Note that CS and CLK are combined with an OR gate, which
controls the serial-to-parallel shift register. These two inputs
are completely interchangeable. In addition, care must be
taken with the state of CLK when CS rises at the end of a
serial transfer. If CLK is LOW when CS rises, the OR gate
will provide a rising edge to the shift register, shifting the
internal data one additional bit. The result will be incorrect
data and possible selection of the wrong input register(s). If
both CS and CLK are used, CS should rise only when CLK
is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table II for more information.
CS
(1)
CLK
(1)
LOAD
RST
SERIAL SHIFT REGISTER
H
(2)
X
(3)
H
H
No Change
L
(4)
L
H
H
No Change
L
↑
↑
(5)
L
H
H
Advanced One Bit
H
H
Advanced One Bit
H
(6)
X
L
(7)
H
No Change
H
(6)
X
H
↑
(8)
No Change
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH.
(3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition.
(6) A HIGH value is suggested in order to avoid a “false clock” from advancing
the shift register and changing the shift register. (7) If data is clocked into the
serial register while LOAD is LOW, the selected DAC register will change as
the shift register bits “flow” through A1 and A0. This will corrupt the data in
each DAC register that has been erroneously selected. (8) Rising edge of RST
causes no change in the contents of the serial shift register.
TABLE II. Serial Shift Register Truth Table.
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