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參數(shù)資料
| 型號： | DAC7801 |
| 英文描述： | Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS |
| 中文描述： | 雙路單片CMOS 12位乘法數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | DAC7801 |
5
DAC7800, 01, 02
DAC7800
(CONT)
TIMING CHARACTERISTICS
V
DD
= +5V, V
REF A
= V
REF B
= +10V, T
A
= –40
°
C to +85
°
C.
DATA
CS
CLK
t
1
t
5
UPD A
UPD B
t
3
t
7
CLR
t
6
t
8
t
4
0V
5V
5V
5V
5V
0V
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns. (2) Tim-
ing measurement reference level isV + V
2
IH
IL
.
t
2
PARAMETER
MINIMUM
t
1
— Data Setup Time
t
2
— Data Hold Time
t
3
— Chip Select to CLK,
Update, Data Setup Time
t
4
— Chip Select to CLK,
Update, Data Hold Time
t
5
— CLK Pulse Width
t
6
— Clear Pulse Width
t
7
— Update Pulse Width
t
8
— CLK Edge to UPD A
or UPD B
15ns
15ns
15ns
40ns
40ns
40ns
40ns
15ns
LOGIC TRUTH TABLE
DAC A
I
AGND A
R
FB A
V
V
R
FB B
I
AGND B
OUT A
REF A
REF B
OUT B
20
V
DD
2
1
3
4
21
22
23
24
DAC A Register
12
4
8
DAC A
LS
Input
Reg
DAC A
MS
Input
Reg
C
DAC B
12
DAC B Register
4
8
12
DGND
DAC B
LS
Input
Reg
DAC B
MS
Input
Reg
19
16
15
5
18
17
UPD
A1
A0
CS
WR
CLR
DAC7801
14
6
DB7–DB0
BLOCK DIAGRAM
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AGND A
CS
DB0
DB1
DB2
DB3
DB4
DB5
DGND
AGND B
I
R
V
V
UPD
WR
CLR
A1
A0
DB7
DB6
OUT A
I
FB A
R
REF A
V
FB B
REF B
DD
OUT B
DAC7801
Top View
DIP
DAC7801
CLR
UPD
CS
WR
A1
A0
FUNCTION
1
1
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
1
X
X
0
0
0
0
1
0
X
1
X
0
0
0
0
0
0
X
X
X
0
0
1
1
X
X
X
X
X
0
1
0
1
X
X
No Data Transfer
No Data Transfer
All Registers Cleared
DAC A LS Input Register Loaded with DB7–DB0 (LSB)
DAC A MS Input Register Loaded with DB3 (MSB)–DB0
DAC B LS Input Register Loaded with DB7–DB0 (LSB)
DAC B MS Input Register Loaded with DB3 (MSB)–DB0
DAC A, DAC B Registers Updated Simultaneously from Input Registers
DAC A, DAC B Registers are Transparent
X = Don’t care.
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