參數(shù)資料
型號: DAC7802K
英文描述: Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS
中文描述: 雙路單片CMOS 12位乘法數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù): 4/12頁
文件大?。?/td> 180K
代理商: DAC7802K
4
DAC7800, 01, 02
DAC7800
BLOCK DIAGRAM
V
DD
DAC A
DAC B
DAC A Register
12
12
12
UPD B
I
AGND B
R
V
V
R
I
AGND A
UPD A
OUT B
FB B
REF B
REF A
FB A
OUT A
12
9
DGND
10
15
16
14
13
4
3
2
1
6
DAC B Register
Bit 0
Bit 11
Bit 12
Bit 23
C
7
11
CLR
12
DAC7800
Data
In
5
CLK
8
CS
PIN CONFIGURATION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AGND A
CLK
UPD A
Data In
CS
AGND B
I
R
V
V
CLR
UPD B
DGND
OUT A
FB A
REF A
OUT B
DAC7800
Top View
DIP
I
R
V
FB B
REF B
DD
Data In
Bit 0
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB
DAC A
MSB
DAC A
LSB
DAC B
MSB
DAC B
DAC7800 Data Input Sequence
DAC7800 Digital Interface Block Diagram
24-Bit
Shift Register
DAC A Register
UPD A
Data In
CLK
UPD B
LSB
MSB
DAC B Register
LSB
MSB
Bit
23
Bit
12
Bit
11
Bit
0
CLK
DATA INPUT FORMAT
CLK
UPD A
UPD B
CS
CLR
FUNCTION
X
X
X
X
X
0
1
0
X
X
X
1
0
0
X
1
0
0
0
0
0
X
1
1
1
1
All register contents set to 0’s (asynchronous).
No data transfer.
Input data is clocked into input register (location Bit 23) and previous data shifts.
Input register bits 23 (LSB)—12 (MSB) are loaded into DAC A.
Input register bits 11 (LSB)—0 (MSB) are loaded into DAC B.
Input register bits 23 (LSB)—12 (MSB) are loaded into DAC A, and input register bits 11 (LSB)—0 (MSB)
are loaded into DAC B.
X
X
X
X = Don’t care.
means falling edge triggered.
LOGIC TRUTH TABLE
相關(guān)PDF資料
PDF描述
DAC7800 Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS
DAC7801 Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS
DAC7802L Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS
DAC7811IDRCT 12-Bit, Serial Input, Multiplying Digital-to-Analog Converter
DAC7811IDRCR 12-Bit, Serial Input, Multiplying Digital-to-Analog Converter
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