參數(shù)資料
型號： DAC7802L
英文描述： Dual Monolithic CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTERS
中文描述： 雙路單片CMOS 12位乘法數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù)： 6/12頁
文件大小： 180K
代理商： DAC7802L
6
DAC7800, 01, 02
CK
DAC B
DAC A
12
12
12
12
12
DGND
18
CS A
5
CS B
20
WR
19
21
V
DD
DAC7802
6
2 I
3 R
OUT A
FB A
23 R
24 I
1 AGND
FB B
OUT B
DAC A Register
CK
DAC B Register
DB11–DB0
4
22
V
V
REF A
REF B
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AGND
I
R
V
CS A
(LSB) DB0
DB1
DB2
DB3
DB4
DB5
DGND
I
R
V
V
CS B
WR
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
FB B
REF B
DD
OUT B
DAC7802
Top View
DIP
TIMING CHARACTERISTICS
At V
DD
= +5V, and T
A
= –40
o
C to +85
o
C.
DATA
5V
0V
5V
5V
CSA, CSB
WR
t
2
t
1
t
3
t
4
t
5
NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. t = t = 5ns. (2) Timing measurement reference level
V + V
2
is
IL
.
PARAMETER
MINIMUM
t
1
- Data Setup Time
t
2
- Data Hold Time
t
3
- Chip Select to Write Setup Time
t
4
- Chip Select to Write Hold Time
t
5
- Write Pulse Width
20ns
15ns
30ns
0ns
30ns
LOGIC TRUTH TABLE
CSA
CSB
WR
FUNCTION
X
X
1
No Data Transfer
1
1
X
No Data Transfer
0
A Rising Edge on CSA or CSB Loads
Data to the Respective DAC
0
1
DAC A Register Loaded from Data Bus
1
0
DAC B Register Loaded from Data Bus
0
0
DAC A and DAC B Registers Loaded
from Data Bus
X = Don’t care.
means rising edge triggered.
PIN CONFIGURATION
DAC7802
DAC7801
(CONT)
TIMING CHARACTERISTICS
V
DD
= +5V, V
REF A
= V
REF B
= +10V, T
A
= –40
°
C to +85
°
C.
PARAMETER
MINIMUM
t
1
— Address Valid to Write Setup Time
t
2
— Address Valid to Write Hold Time
t
3
— Data Setup Time
t
4
— Data Hold Time
t
5
— Chip Select or Update to Write Setup Time
t
6
— Chip Select or Update to Write Hold Time
t
7
— Write Pulse Width
t
8
— Clear Pulse Width
10ns
10ns
30ns
10ns
0ns
0ns
40ns
40ns
A0–A1
CLR
t
2
t
1
t
8
WR
t
7
CS, UPD
t
6
t
4
t
3
DATA
t
5
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t = t = 5ns. (2) Timing measurement reference level is
V + V
2
IL
.
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