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參數(shù)資料
| 型號： | DAC7811IDRCR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-Bit, Serial Input, Multiplying Digital-to-Analog Converter |
| 中文描述： | 12位，串行輸入，乘法數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 698K |
| 代理商： | DAC7811IDRCR |
www.ti.com
P
SYNC Interrupt
Daisy-Chain
t
CSS
t
CH
t
DS
t
DH
t
DDS
t
CC
t
CST
t
9
t
C
SCLK
SYNC
SDIN
DB15
(N)
DB0
(N)
DB15
(N)
DB0
(N)
DB15
(N + 1)
DB0
(N + 1)
SDO
Control Bits C3 to C0
DAC7811
SBAS337–APRIL 2005
In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is
updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an
interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an
update of the DAC register contents or a change in the operating mode occurs.
The DAC7811 powers up in the daisy chain mode which must be used when 2 or more devices are connected in
tandem. The SCLK and SYNC signals are shared across all devices while the SDO output of the first device
connects to the SDIN input of the following device, and so forth. In this configuration 16 SCLK cycles for each
DAC7811 in the chain are required. Please refer to the timing diagram of Figure 28.
For
n
devices in a daisy-chain configuration, 16
n
SCLK cycles are required to shift in the entire input data
stream. After 16
n
active SCLK edges are received following a falling SYNC, the data stream becomes complete,
and SYNC can brought high to update n devices simultaneously.
When SYNC is brought high, each device will execute the function defined by the four DAC control bits C3-C0 in
its input shift register. For example, C3-C0 must be
0001
for each DAC in the chain that is to be updated with
new data, and C3-C0 must be
0000
for each DAC in the chain whose contents are to remain unchanged.
A continuous stream containing the exact number of SCLK cycles may be sent first while the SYNC signal is held
low, and then raise SYNC at a later time. Nothing happens until the rising edge of SYNC, and then each
DAC7811 in the chain will execute the function defined by the four DAC control bits C3-C0 in its input shift
register.
Figure 28. DAC7811 Timing Diagram
Control Bits C3 to C0 allow control of various functions of the DAC; see Table 3. Default settings of the DAC on
powering up are as follows: Data clocked into shift register on falling clock edges; daisy-chain mode is enabled.
Device powers on with zero-scale loaded into the DAC register and IOUT lines. The DAC control bits allow the
user to adjust certain features as part of an initialization sequence, for example, daisy-chaining may be disabled
if not in use, active clock edge may be changed to rising edge, and DAC output may be cleared to either zero or
midscale. The user may also initiate a readback of the DAC register contents for verification purposes.
11
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC7811IDRCT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-Bit, Serial Input, Multiplying Digital-to-Analog Converter |
| DAC7821 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-Bit, Parallel Input, Multiplying Digital-to-Analog Converter |
| DAC7821IPW | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Parallel Inp Multiplying DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7821IPW | 制造商:Texas Instruments 功能描述:D/A CONVERTER (D-A) IC |
| DAC7821IPWG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-bit Parallel Inp Multiplying DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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