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參數(shù)資料
| 型號(hào)： | DAC7811IDRCT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-Bit, Serial Input, Multiplying Digital-to-Analog Converter |
| 中文描述： | 12位，串行輸入，乘法數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大?。?/td> | 698K |
| 代理商： | DAC7811IDRCT |
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P
PIN DESCRIPTIONS
MSOP PACKAGE
(TOP VIEW)
1
2
3
4
5
10
9
8
7
6
I
OUT
1
I
OUT
2
GND
SCLK
SDIN
R
FB
V
REF
V
DD
SDO
SYNC
R
FB
V
REF
V
DD
SDO
SYNC
10
9
8
7
6
I
OUT
1
I
OUT
2
GND
SCLK
SDIN
1
2
3
4
5
SON PACKAGE
3mm x 3mm QFN
(TOP VIEW)
DAC7811
SBAS337–APRIL 2005
Table 1. TERMINAL FUNCTIONS
TERMINAL
NO.
1
2
3
DESCRIPTION
NAME
I
OUT
1
I
OUT
2
GND
DAC Current Output
DAC Analog Ground. This pin is normally tied to the analog ground of the system.
Ground pin.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input.
Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift
register on the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default,
on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to
change the active edge to the rising edge.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers
on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active
edge of the following clocks (power-on default is falling clock edge). In stand-alone mode, the serial interface counts
the clocks and data is latched to the shift register on the 16th active clock edge.
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift register
on the falling edge and out via SDO on the rising edge of SCLK. Data will always be clocked out on the alternate edge
to loading data to the shift register. Writing the Readback control word to the shift register makes the DAC register
contents available for readback on the SDO pin, clocked out on the opposite edges to the active clock edge.
Positive Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
DAC Reference Voltage Input
DAC Feedback Resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
4
SCLK
5
SDIN
6
SYNC
7
SDO
8
9
10
V
DD
V
REF
R
FB
4
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