參數(shù)資料
型號: DAC8043HP
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 12-Bit Serial Input Multiplying CMOS D/A Converter
中文描述: SERIAL INPUT LOADING, 0.25 us SETTLING TIME, 12-BIT DAC, PDIP8
封裝: MINI, PLASTIC, DIP-8
文件頁數(shù): 8/12頁
文件大?。?/td> 189K
代理商: DAC8043HP
DAC8043
–8–
REV. C
Figure 6. Unipolar Operation with Fast Op Amp and Gain
Error Trimming (2-Quadrant)
the analog output is shown in T able I. T he limiting parameters
for the V
REF
range are the maximum input voltage range of the
op amp or
±
25 V, whichever is lowest.
Gain error may be trimmed by adjusting R
1
as shown in Figure
6. T he DAC register must first be loaded with all 1s. R
1
may
then be adjusted until V
OUT
= –V
REF
(4095/4096). In the case of
an adjustable V
REF
, R
1
and R
2
may be omitted, with V
REF
ad-
justed to yield the desired full-scale output.
In most applications the DAC8043’s negligible zero scale error
and very low gain error permit the elimination of the trimming
components (R
1
and the external R
2
) without adverse effects on
circuit performance.
T he gain and phase stability of the output amplifier, board lay-
out, and power supply decoupling will all affect the dynamic
performance. T he use of a small compensation capacitor may be
required when high-speed operational amplifiers are used. It
may be connected across the amplifier’s feedback resistor to
provide the necessary phase compensation to critically damp the
output. T he DAC8043’s output capacitance and the R
FB
resis-
tor form a pole that must be outside the amplifier’s unity gain
crossover frequency.
T he considerations when using high-speed amplifiers are:
1. Phase compensation (see Figures 5 and 6).
2. Power supply decoupling at the device socket and use of
proper grounding techniques.
APPLICAT IONS INFORMAT ION
APPLICAT ION T IPS
In most applications, linearity depends upon the potential of
I
OUT
and GND (pins 3 and 4) being exactly equal to each other.
In most applications, the DAC is connected to an external op
amp with its noninverting input tied to ground (see Figures 5
and 6). T he amplifier selected should have a low input bias cur-
rent and low drift over temperature. T he amplifier’s input offset
voltage should be nulled to less than +200
μ
V (less than 10% of
1 LSB).
T he operational amplifier’s noninverting input should have a
minimum resistance connection to ground; the usual bias cur-
rent compensation resistor should not be used. T his resistor can
cause a variable offset voltage appearing as a varying output er-
ror. All grounded pins should tie to a single common ground
point, avoiding ground loops. T he V
DD
power supply should
have a low noise level with no transients greater than +17 V.
UNIPOLAR OPE RAT ION (2-QUADRANT )
T he circuit shown in Figures 5 and 6 may be used with an ac or
dc reference voltage. T he circuit’s output will range between 0 V
and approximately –V
REF
(4095/4096) depending upon the digital
input code. T he relationship between the digital input and
Figure 5. Unipolar Operation with High Accuracy Op Amp
(2-Quadrant)
T able I. Unipolar Code T able
Digital Input
MSB
Nominal Analog Output
(V
OUT
as shown in Figures 5 and 6)
LSB
1111 1111 1111
–V
REF
4095
4096
1000 0000 0001
–V
REF
2049
4096
1000 0000 0000
–V
REF
2048
4096
= –
V
REF
2
0111 1111 1111
–V
REF
2047
4096
0000 0000 0001
–V
REF
1
4096
0
4096
=
0
0000 0000 0000
–V
REF
NOT ES
1
Nominal full scale for the circuits of Figures 5 and 6 is given by
FS = –V
REF
4095
4096
2
Nominal LSB magnitude for the circuits of Figures 5 and 6 is given by
LSB = V
REF
1
4096
or V
REF
(2
–n
).
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