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參數(shù)資料
| 型號(hào)： | DAC811RH |
| 英文描述： | Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 微處理器兼容的12位數(shù)字到模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大小： | 96K |
| 代理商： | DAC811RH |
DAC811
4
TIMING DIAGRAMS
DISCUSSION OF
SPECIFICATIONS
INPUT CODES
The DAC811 accepts positive-true binary input codes.
DAC811 may be connected by the user for any one of the
following codes: USB (unipolar straight binary), BOB (bi-
polar offset binary) or, using an external inverter on the
MSB line, BTC (binary two’s complement). See Table I.
DRIFT
Gain drift is a measure of the change in the full scale range
(FSR) output over the specification temperature range. Drift is
expressed in parts per million per degree centigrade
(ppm/
°
C). Gain drift is established by testing the full scale
range value (e.g., +FS minus –FS) at high temperature, +25
°
C,
and low temperature, calculating the error with respect to the
+25
°
C value, and dividing by the temperature change.
Unipolar offset drift is a measure of the change in output
with all 0s on the input over the specification temperature
range. Offset is measured at high temperature, +25
°
C, and
low temperature. The offset drift is the maximum change in
offset referred to the +25
°
C value, divided by the tempera-
ture change. It is expressed in parts per million of full scale
range per degree centigrade (ppm of FSR/
°
C).
Bipolar zero drift is measured at a digital input of 800
16
, the
code that gives zero volts output for bipolar operation.
SETTLING TIME
Settling time is the total time (including slew time) for the
output to settle within an error band around its final value
after a change in input. Three settling times are specified to
±
0.01% of full scale range (FSR): two for maximum full
scale range changes of 20V and 10V, and one for a 1LSB
change. The 1LSB change is measured at the major carry
(7FF
16
to 800
16
and 800
16
to 7FF
16
), the input transition at
which worst-case settling time occurs.
REFERENCE SUPPLY
DAC811 contains an on-chip 6.3V reference. This voltage
(pin 28) has a tolerance of
±
0.1V. The reference output may
be used to drive external loads, sourcing at least 2mA. This
current should be constant for best performance of the D/A
converter.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
power supply change on the D/A converter output. It is
defined as a percent of FSR output change per percent of
change in either the positive, negative, or logic supply
voltages about the nominal voltages. Figure 1 shows typical
power supply rejection versus power supply ripple frequency.
DIGITAL INPUT
ANALOG OUTPUT
USB
Unipolar
Straight
Binary
BOB
Bipolar
Offset
Binary
BTC
(1)
Binary
Two’s
Complement
111111111111
100000000000
011111111111
000000000000
+ Full Scale
+ 1/2 Full Scale
+ 1/2 Full Scale – 1LSB
Zero
+ Full Scale
Zero
–1LSB
– Full Scale
–1LSB
– Full Scale
+ Full Scale
Zero
NOTE: (1) Invert MSB of the BOB code with external inverter to obtain BTC code.
MSB
↓
LSB
↓
TABLE I. Digital Input Codes.
LINEARITY ERROR
Linearity error as used in D/A converter specifications by
Burr-Brown is the deviation of the analog output from a
straight line drawn between the end points (inputs all 1s and
all 0s). The DAC811 linearity error is specified at
±
1/4LSB
(max) at +25
°
C for B and K grades, and
±
1/2LSB (max) for
A, J, and R grades.
DIFFERENTIAL LINEARITY ERROR
Differential linearity error (DLE) is the deviation from a
1LSB output change from one adjacent state to the next. A
DLE specification of 1/2LSB means that the output step size
can range from 1/2LSB to 3/2LSB when the input changes
from one state to the next. Monotonicity requires that DLE
be less than 1LSB over the temperature range of interest.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital inputs. All grades
of DAC811 are monotonic over their specification tempera-
ture range.
Load first rank from Data Bus: LDAC = 1
WR
N
t
AW
t
DW
t
DH
t
WP
A
, N
B
, N
C
DB
11
–DB
0
Write Cycle #1
t
SET
WR
±
1/2LSB
LDAC
t
AW
t
WP
Load second rank from first rank: N
A
, N , N
C
= 1
Write Cycle #2
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