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參數(shù)資料
| 型號： | DAC8248GPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL W/BUFF 24DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 15 |
| 設(shè)置時間： | 1µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 1M |
DAC8248
–11–
REV. B
AUTOMATIC DATA TRANSFER MODE
Data may be transferred automatically from the input register to
the DAC register. The first cycle loads the first data byte into
the input register; the second cycle loads the second data byte
and simultaneously transfers the full 12-bit data word to the
DAC register. It takes four cycles to load and transfer two com-
plete digital words for both DAC’s, see Figure 4 (Four Cycle
Update Timing Diagram) and the Mode Selection Table.
STROBED DATA TRANSFER MODE
Strobed data transfer allows the full 12-bit digital word to be
loaded into the input registers and transferred to the DAC regis-
ters at a later time. This transfer mode requires five cycles: four
to load two new data words into both DACs, and the fifth to
transfer all data into the DAC registers. See Figure 5 (Five Cycle
Update Timing Diagram) and the Mode Selection Table.
Strobed data transfer separating data loading and transfer op-
erations serves two functions: the DAC output updating may be
more precisely controlled, and multiple DACs in a multiple
DAC system can be updated simultaneously.
RESET
The DAC8248 comes with a RESET pin that is useful in system
calibration cycles and/or during system power-up. All registers
are reset to zero when RESET is low, and latched at zero on the
rising edge of the RESET signal when WRITE is high.
INTERFACE CONTROL LOGIC
The DAC8248’s control logic is shown in Figure 6. This cir-
cuitry interfaces with the system bus and controls the DAC
functions.
Figure 6. Input Control Logic
MODE SELECTION TABLE
DIGITAL INPUTS
REGISTER STATUS
DAC A
DAC B
Input Register
DAC
Input Register
DAC
DAC A
/B
WR
LSB
/MSB
RESET
LDAC
LSB
MSB
Register
LSB
MSB
Register
L
H
WR
LAT
L
H
L
WR
LAT
WR
LAT
WR
L
H
LAT
WR
LAT
L
H
L
LAT
WR
LAT
WR
H
L
H
LAT
WR
LAT
H
L
H
L
LAT
WR
LAT
WR
H
L
H
LAT
WR
LAT
H
L
H
L
LAT
WR
LAT
WR
X
H
X
H
LAT
X
H
X
H
L
LAT
WR
LAT
WR
X
L
X
ALL REGISTERS ARE RESET TO ZEROS
XH
X
g
X
ZEROS ARE LATCHED IN ALL REGISTERS
L = Low, H = High, X = Don’t Care, WR = Registers Being Loaded, LAT = Registers Latched.
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