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參數(shù)資料
| 型號： | DAC8408GPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 0.19 us SETTLING TIME, 8-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 219K |
| 代理商： | DAC8408GPZ |
DAC8408
–11–
REV. A
Figure 7. Quad DAC Bipolar Operation (4-Quadrant Multiplication)
Table II. Bipolar (Offset Binary) Code Table
(Refer to Figure 7)
DAC Data Input
Analog Output
MSB
LSB
(DAC A OR DAC B)
1 1 1 1 1 1 1 1
+VREF
127
128
1 0 0 0 0 0 0 1
+VREF
1
128
1 0 0 0 0 0 0 0
0
0 1 1 1 1 1 1 1
–VREF
1
128
0 0 0 0 0 0 0 1
–VREF
127
128
0 0 0 0 0 0 0 0
–VREF
128
NOTE
1 LSB = (2
–7) (V
REF) =
1
128
(VREF)
APPLICATION HINTS
General Ground Management: AC or transient voltages be-
tween AGND and DGND can appear as noise at the DAC8408’s
analog output. Note that in Figures 5 and 6, IOUT2A/IOUT2B and
IOUT 2C/IOUT 2D are connected to AGND. Therefore, it is rec-
ommended that AGND and DGND be tied together at the
DAC8408 socket. In systems where AGND and DGND are tied
together on the backplane, two diodes (1N914 or equivalent)
should be connected in inverse parallel between AGND and
DGND.
Write Enable Timing: During the period when both DS and
R/W are held low, the DAC latches are transparent and the ana-
log output responds directly to the digital data input. To pre-
vent unwanted variations of the analog output, the R/W should
not go low until the data bus is fully settled (DATA VALID).
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