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參數(shù)資料
| 型號： | DAC8412EP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Quad, 12-Bit DAC Voltage Output with Readback |
| 中文描述： | QUAD, PARALLEL, WORD INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, MS-001, DIP-28 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 443K |
| 代理商： | DAC8412EP |
DAC8412/DAC8413
–11–
REV. D
Table I. DAC8412/DAC8413 Logic Table
A1
A0
R/
W
CS
RS
LDAC
INPUT REG
OUTPUT REG
MODE
DAC
L
L
H
H
L
L
H
H
L
L
H
H
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
L
L
L
L
L
L
L
L
H
H
H
H
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
g
L
L
L
L
H
H
H
H
H
H
H
H
L
H
X
X
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
READ
READ
READ
READ
HOLD
HOLD
*All registers reset to mid/zero-scale
*All registers latched to mid/zero-scale
WRITE
WRITE
WRITE
WRITE
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
HOLD
Update all output registers
HOLD
Transparent
Transparent
Transparent
Transparent
WRITE INPUT
WRITE INPUT
WRITE INPUT
WRITE INPUT
READ INPUT
READ INPUT
READ INPUT
READ INPUT
A
B
C
D
A
B
C
D
A
B
C
D
All
All
All
All
HOLD
*DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = Logic Low; H = Logic High; X - Don’t Care. Input and Output registers are transparent when
asserted.
The R/
W
input, when enabled by
CS
, controls the writing to and
reading from the input register.
Coding
Both the DAC8412 and DAC8413 use binary coding. The out-
put voltage can be calculated by:
V
V
V
(
V
N
OUT
REFL
REFH
REFL
=
+
×
_
4096
)
where
N
is
the digital code in decimal.
RESET
The
RESET
function can be used either at power-up or at any
time during the DAC
’
s operation. The
RESET
function is inde-
pendent of
CS
. This pin is active LOW and sets the DAC output
registers to either center code for the DAC8412, or zero code
for the DAC8413. The reset to center code is most useful when
the DAC is configured for bipolar references and an output of
zero volts after reset is desired.
Supplies
Supplies required are V
SS
, V
DD
and V
LOGIC
. The V
SS
supply can
be set between
–
15 V and 0 V. V
DD
is the positive supply; its op-
erating range is between +5 V and +15 V.
V
LOGIC
is the digital output supply voltage for the readback
function. It is normally connected to +5 V. This pin is a logic
reference input only. It does not supply current to the device.
If you are not using the readback function, V
LOGIC
can be left open-
circuit.
While V
LOGIC
does not supply current to the DAC8412,
it does supply currents to the digital outputs when readback
is used.
Amplifiers
Unlike many voltage output DACs, the DAC8412 features buff-
ered voltage outputs. Each output is capable of both sourcing
and sinking 5 mA at
±
10 volts, eliminating the need for external
amplifiers when driving 500 pF or smaller capacitive load in
most applications. These amplifiers are short-circuit protected.
Reference Inputs
All four DACs share common reference high (V
REFH
) and refer-
ence low (V
REFL
) inputs. The voltages applied to these reference
inputs set the output high and low voltage limits of all four of
the DACs. Each reference input has voltage restrictions with
respect to the other reference and to the power supplies. The
V
REFL
can be set at any voltage between V
SS
and V
REFH
–
2.5 V,
and V
REFH
can be set to any value between +V
DD
–
2.5 V and
V
REFL
+ 2.5 V. Note that because of these restrictions the
DAC8412 references cannot be inverted (i.e., V
REFL
cannot be
greater than V
REFH
).
It is important to note that the DAC8412
’
s V
REFH
input both
sinks and sources current. Also the input current of both V
REFH
and V
REFL
are code dependent. Many references have limited
current sinking capability and must be buffered with an ampli-
fier to drive V
REFH
. The V
REFL
has no such special requirements.
It is recommended that the reference inputs be bypassed with
0.2
μ
F capacitors when operating with
±
10 V references. This
limits the reference bandwidth.
Digital I/O
See Table I for digital control logic truth table. Digital I/O consists
of a 12-bit bidirectional data bus, two registers select inputs, A0
and A1, a R/
W
input, a
RESET
input, a Chip Select (
CS
), and
a Load DAC (
LDAC
) input. Control of the DACs and bus
direction is determined by these inputs as shown in Table I.
Digital data bits are labeled with the MSB defined as data bit
“
11
”
and the LSB as data bit
“
0.
”
All digital pins are TTL/
CMOS compatible.
See Figure 35 for a simplified I/O logic diagram. The register
select inputs A0 and A1 select individual DAC registers
“
A
”
(binary code 00) through
“
D
”
(binary code 11). Decoding of
the registers is enabled by the
CS
input. When
CS
is high no
decoding takes place, and neither the writing nor the reading of
the input registers is enabled. The loading of the second bank of
registers is controlled by the asynchronous
LDAC
input. By tak-
ing
LDAC
low while
CS
is enabled, all output registers can be
updated simultaneously. Note that the t
LDW
required pulsewidth
for updating all DACs is a minimum of 170 ns.
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