參數(shù)資料
型號(hào)： DAC8412FPC
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Quad, 12-Bit DAC Voltage Output with Readback
中文描述： QUAD, PARALLEL, WORD INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, PQCC28
封裝： PLASTIC, MO-047AB, LCC-28
文件頁數(shù)： 3/14頁
文件大?。?/td> 443K
代理商： DAC8412FPC
–3–
REV. D
DAC8412/DAC8413
(@ V
DD
= V
LOGIC
= +5.0 V 5%, V
SS
= 0.0 V, V
REFH
= +2.5 V, V
REFL
= 0.0 V, and V
SS
= –5.0 V 5%,
V
REFL
= –2.5 V, –40 C
≤
T
A
≤
+85 C unless otherwise noted. See Note 1 for supply variations.)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
±
1
±
2
±
2
±
4
Units
Integral Nonlinearity Error
INL
INL
INL
INL
DNL
V
ZSE
V
FSE
V
ZSE
V
FSE
TCV
ZSE
TCV
FSE
E Grade
F Grade
V
SS
= 0.0 V; E Grade
2
V
SS
= 0.0 V; F Grade
2
Monotonic Over Temperature
V
SS
= –5.0 V
V
SS
= –5.0 V
V
SS
= 0.0 V
V
SS
= 0.0 V
1/2
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/
°
C
ppm/
°
C
LSB
Differential Nonlinearity Error
Min-Scale Error
Full-Scale Error
Min-Scale Error
Full-Scale Error
Min-Scale Tempco
Full-Scale Tempco
Linearity Matching
REFERENCE
Positive Reference Input Voltage Range
Negative Reference Input Voltage Range
–1
±
4
±
4
±
8
±
8
100
100
±
1
Adjacent DAC Matching
Note 3
V
SS
= 0.0 V
V
SS
= –5.0 V
Code 000H
–3 dB, V
REFH
= 0 V to 2.5 V p-p
V
REFL
+ 2.5
0
–2.5
–1.0
V
DD
– 2.5
V
REFH
– 2.5 V
V
REFH
– 2.5 V
+1.0
V
Reference High Input Current
Large Signal Bandwidth
AMPLIFIER CHARACTERISTICS
Output Current
Settling Time
Slew Rate
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Output High Voltage
Logic Output Low Voltage
Logic Input Current
Input Capacitance
LOGIC TIMING CHARACTERISTICS
4
Chip Select Write Pulsewidth
Write Setup
Write Hold
Address Setup
Address Hold
Load Setup
Load Hold
Write Data Setup
Write Data Hold
Load Data Pulsewidth
Reset Pulsewidth
Chip Select Read Pulsewidth
Read Data Hold
Read Data Setup
Data to Hi Z
Chip Select to Data
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Negative Supply Current
Power Dissipation
I
REFH
BW
mA
kHz
450
I
OUT
t
S
SR
R
L
= 2 k
, C
L
= 100 pF
to 0.01%, 2.5 V Step, R
L
= 1 k
10% to 90%
–1.25
+1.25
mA
μ
s
V/
μ
s
7
2.2
V
INH
V
INL
V
OH
V
OL
I
IN
C
IN
T
A
= +25
°
C
T
A
= +25
°
C
I
OH
= +0.4 mA
I
OL
= –1.6 mA
2.4
V
V
V
V
μ
A
pF
0.8
2.4
0.45
1
8
Note 5
t
WCS
t
WS
t
WH
t
AS
t
AH
t
LS
t
LH
t
WDS
t
WDH
t
LDW
t
RESET
t
RCS
t
RDH
t
RDS
t
DZ
t
CSD
150
0
0
0
0
70
50
20
0
180
150
170
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WCS
= 150 ns
t
WCS
= 150 ns
t
WCS
= 150 ns
t
WCS
= 150 ns
t
RCS
= 170 ns
t
RCS
= 170 ns
C
L
= 10 pF
C
L
= 100 pF
200
320
PSS
I
DD
I
SS
P
DISS
100
7
ppm/V
mA
mA
mW
mW
12
V
SS
= –5.0 V
V
SS
= 0 V
V
SS
= –5 V
–10
60
110
NOTES
1
All supplies can be varied
±
5%, and operation is guaranteed. Device is tested with V
= +4.75 V.
2
For single supply operation only (V
= 0.0 V, V
= 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002
H
).
3
Operation
is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4
All parameters are guaranteed by design.
5
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Specifications subject to change without notice.
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