參數(shù)資料
型號(hào)： DAC8412FPC
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/20頁(yè)
文件大小： 0K
描述： IC DAC 12BIT QUAD READBK 28-PLCC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： DAC8412/3 Redesign and Fab Process Change 01/Oct/2009
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
功率耗散（最大）： 330mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 167k
DAC8412/DAC8413
Data Sheet
Rev. G | Page 14 of 20
THEORY OF OPERATION
INTRODUCTION
The DAC8412/DAC8413 are quad, voltage output, 12-bit parallel
input DACs featuring a 12-bit data bus with readback capability.
The only differences between the DAC8412/DAC8413 are the
reset functions. The DAC8412 resets to midscale (Code 0x800),
and the DAC8413 resets to minimum scale (Code 0x000).
The ability to operate from a single 5 V supply is a unique
feature of these DACs.
Operation of the DAC8412/DAC8413 can be viewed by
dividing the system into three separate functional groups: the
digital I/O and logic, the digital-to-analog converters, and the
output amplifiers.
DACS
Each DAC is a voltage switched, high impedance (R = 50 kΩ),
R-2R ladder configuration. Each 2R resistor is driven by a pair
of switches that connect the resistor to either VREFH or VREFL.
GLITCH
Worst-case glitch occurs at the transition between Half-Scale
Digital Code 1000 0000 0000 to half-scale minus 1 LSB, 0111
1111 1111. It can be measured at about 2 V μs (see Figure 36).
For demanding applications such as waveform generation or
precision instrumentation control, a deglitcher circuit can be
implemented with a standard sample-and-hold circuit (see
Figure 37). When CS is enabled by synchronizing the hold
period to be longer than the glitch tradition, the output voltage
can be smoothed with minimum disturbance. A quad
sample-and-hold amplifier, SMP04, has been used to illustrate
the deglitching result (see Figure 36).
S/H
CS
DACOUT1
DACOUT
DACOUT1
S/H
HS
H
S
00
27
4
-03
8
Figure 37. Data Output (Read Timing)
REFERENCE INPUTS
All four DACs share common reference high (VREFH) and reference
low (VREFL) inputs. The voltages applied to these reference inputs set
the output high and low voltage limits of all four of the DACs.
Each reference input has voltage restrictions with respect to the
other reference and to the power supplies. The VREFL can be set at
any voltage between VSS and VREFH 2.5 V, and VREFH can be set to
any value between +VDD 2.5 V and VREFL + 2.5 V. Note that
because of these restrictions, the DAC8412 references cannot be
inverted (that is, VREFL cannot be greater than VREFH).
It is important to note that the DAC8412 VREFH input both sinks
and sources current. In addition, the input current of both VREFH
and VREFL are code-dependent. Many references have limited
current-sinking capability and must be buffered with an
amplifier to drive VREFH. The VREFL has no such special
requirements.
It is recommended that the reference inputs be bypassed with
0.2 μF capacitors when operating with ±10 V references. This
limits the reference bandwidth.
DIGITAL I/O
See Table 6 for the digital control logic truth table. Digital I/O
consists of a 12-bit bidirectional data bus, two registers select
inputs, A0 and A1, a R/W input, a RESET input, a chip select (CS),
and a load DAC (LDAC) input. Control of the DACs and bus
direction is determined by these inputs as shown in Table 6. Digital
data bits are labeled with the MSB defined as Data Bit 11 and the
LSB as Data Bit 0. All digital pins are TTL/CMOS compatible.
See Figure 38 for a simplified I/O logic diagram. The register
select inputs A0 and A1 select individual DAC registers A
(Binary Code 00) through D (Binary Code 11). Decoding of the
registers is enabled by the CS input. When CS is high, no
decoding takes place, and neither the writing nor the reading of
the input registers is enabled. The loading of the second bank of
registers is controlled by the asynchronous LDAC input. By
taking LDAC low while CS is enabled, all output registers can
be updated simultaneously. Note that the tLDW required pulse
width for updating all DACs is a minimum of 170 ns.
The R/W input, when enabled by CS, controls the writing to
and reading from the input register.
CODING
Both DAC8412/DAC8413 use binary coding. The output
voltage can be calculated by
4096
)
(
N
V
REFL
REFH
REFL
OUT
where N is the digital code in decimal.
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