參數(shù)資料
型號： DAC8413FP
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Quad, 12-Bit DAC Voltage Output with Readback
中文描述： QUAD, PARALLEL, WORD INPUT LOADING, 10 us SETTLING TIME, 12-BIT DAC, PDIP28
封裝： PLASTIC, MS-001, DIP-28
文件頁數(shù)： 10/14頁
文件大?。?/td> 443K
代理商： DAC8413FP
DAC8412/DAC8413
–10–
REV. D
10000
1
1000
100
10
NOISE FREQUENCY
–
Hz
10.0
N
–
V
DD
= +15V
V
SS
=
–
15V
V
REFH
= +10V
V
REFL
=
–
10V
T
A
= +25 C
0.10
0.001
1.00
0.01
Figure 29. DAC8412 Noise
Frequency vs. Noise Density
0
0
–
25
–
20
25
–
20
–
30
0
–
10
10
20
30
20
15
10
5
0
–
5
V
OUT
–
Volts
–
10
–
15
I
O
–
V
DD
= +15V
V
SS
=
–
15V
V
REFH
= +10V
V
REFL
=
–
10V
T
DATA = 000
H
+I
SC
–
I
SC
Figure 30. I
OUT
vs. V
OUT
V
DD
= +15V
V
SS
=
–
15V
V
REFH
= +10V
V
REFL
=
–
10V
T
A
= +25 C
CH1 MEAN
66.19 V
M 200 s
A CH1 12.9mV
20uV/DIV
1
Figure 31. Broadband Noise
OPERATION
Introduction
The DAC8412 and DAC8413 are quad, voltage output, 12-bit
parallel input DACs featuring a 12-bit data bus with readback
capability. The only differences between the DAC8412 and
DAC8413 are the reset functions. The DAC8412 resets to mid-
scale (code 800
H
) and the DAC8413 resets to minimum scale
(code 000
H
).
The ability to operate from a single +5 V supply is a unique fea-
ture of these DACs.
Operation of the DAC8412 and DAC8413 can be viewed by
dividing the system into three separate functional groups: the
digital I/O and logic, the digital to analog converters and the output
amplifiers.
DACs
Each DAC is a voltage switched, high impedance (R = 50 k
),
R-2R ladder configuration. Each 2R resistor is driven by a pair of
switches that connect the resistor to either V
REFH
or V
REFL
.
Glitch
Worst-case glitch occurs at the transition between half-scale
digital code 1000 0000 0000 to half-scale minus 1 LSB, 0111
1111 1111. It can be measured at about 2 V
μ
s. (See Figure 33.)
For demanding applications such as waveform generation or
precision instrumentation control, a deglitcher circuit can be
implemented with a standard sample-and-hold circuit. (See
Figure 34.) When
CS
is enabled by synchronizing the hold
period to be longer than the glitch tradition, the output voltage
can be smoothed with minimum disturbance. A quad sample-
and-hold amplifier, SMP04, has been used to illustrate the
deglitching result. (See Figure 33.)
H
S
H
S
S/H
CS
DACOUT'
DACOUT
DACOUT
DACOUT'
S/H
Figure 34. Deglitcher Circuit
–
I
SC
6
–
6
5
25
I
O
–
V
OUT
–
Volts
V
DD
= +15V
V
SS
= 0V
V
REFH
= +10V
V
REFL
= 0V
T
= +25 C
DATA = 800
H
15
–
5
–
15
–
25
20
10
0
–
10
–
20
–
4
–
2
0
2
4
+I
SC
Figure 32. I
OUT
vs. V
OUT
4 s
1V
1V
GLITCH AT DAC OUTPUT
DEGLITCHER OUTPUT
CH2 1.86V
2
1
10 s
Figure 33. Glitch and Deglitched Results
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