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參數(shù)資料
| 型號(hào)： | DAC8426FP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | Quad 8-Bit Voltage Out CMOS DAC Complete with Internal 10 V Reference |
| 中文描述： | QUAD, PARALLEL, 8 BITS INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 289K |
| 代理商： | DAC8426FP |
DAC8426
–9–
REV. C
APPLICAT IONS SE T UP
UNIPOLAR OUT PUT OPE RAT ION
T he output voltage appearing at any output V
OUT
is equal to the
internal 10 V reference multiplied by the decimal value of the
latched digital input divided by 2
8
(= 256). In equation form:
V
OUT
(
D
) =
D
/256
×
10
V
where
D
= 0
10
to
255
10
Figure 4. Amplifier Output Stage
Note that the maximum possible output is 1 LSB less than the
internal 10 V reference, that is, 255/256
×
10 V = 9.961 V.
T able II lists output voltages for a given digital input. T he total
unadjusted error (T UE) specification of the product grade used
determines the output tolerances of the values listed in T able II.
For example, a
±
2 LSB grade DAC8426FP loaded with decimal
128
10
(half-scale) would have a guaranteed output voltage oc-
curring in the range of 5 V
±
2 LSB, which is 5 V
±
(2
×
10 V/256)
= 5 V
±
0.078 V. T herefore V
OUT
is guaranteed to occur in the
following range:
4.922
V
≤
V
OUT
(
128
)
≤
5.078
V
Figure 5. DAC Output Current Sink
For the top grade DAC8426EP
±
1 LSB total unadjusted error
(T UE), the guaranteed range is 4.961 V
≤
V
OUT
(128
10
)
≤
5.039 V.
T hese tolerances provide the worst case analysis including tem-
perature changes.
One additional characteristic guaranteed is a DNL of
±
1 LSB
on all grades. T he DAC8426 is therefore guaranteed to be mon-
otonic. In the situation where a continuously positive 1 LSB
digital increment is applied, the output voltage will always in-
crease in value, never decrease. T his is very important is servo
applications and other closed-loop feedback systems. Finally, in
the typical characteristic curves, long term output voltage drift
(stability) is provided.
BIPOLAR OUT PUT OPE RAT ION
An external op amp plus two resistors can easily convert any
DAC output to bipolar output voltage swings. Figure 6 shows all
four DACs output operating in bipolar mode. T his is the general
expression describing the bipolar output transfer equation:
V
OUT
(
D
) = [(1 +
R
2
/
R
1
)
×
D
/256
×
10
V
] –
R
2
/R
1
×
10
V
,
where
D
= 0
10
to 255
10
If
R
1
= R
2
, then
V
OUT
becomes:
V
OUT
(
D
) = (
D
/128–1)
×
10
V
T able III lists various output voltages with R
1
= R
2
versus digital
input code. T his coding is considered offset binary. Note that
the LSB step size is now 20 V/256 = 0.078 V, twice as large as
the unipolar output case previously discussed. In order to minimize
gain and offset errors, choose R
1
and R
2
to match and track
within 0.1% over the selected operating temperature range
of interest.
T able II. Unipolar Output Voltage as a Function of
Digital Input Code
Digital Input
Code
Analog Output
Voltage (= D/256
×
10 V)
255
254
129
128
127
1
0
9.961 V
9.922 V
5.039 V
5.000 V
4.961 V
0.039 V
0.000 V
Full-Scale (FS)
FS-1 LSB
Half-Scale
1 LSB
Zero-Scale
OFFSE T T ING AGND
Since the DAC ladder and bandgap reference are terminated at
AGND, it is possible to offset AGND positive with respect to
DGND. T he 10 V output span remains if a positive offset is ap-
plied to AGND. T he offset voltage source connected to AGND
must be capable of sinking 14 mA. AGND cannot be taken
negative with respect to DGND; this would forward bias an in-
ternal diode. Allowance must be made at V
DD
to maintain 3.5 V
of headroom above V
REF
OUT . T his connection setup is useful
in single supply applications where virtual ground needs to be
slightly positive with respect to ground. In this application con-
nect V
SS
to DGND to take advantage of the extra buffer output
current sinking capability when the DAC output is programmed
to all zeros code, see Figure 7.
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